ADV7301AKST

ADV7301AKST Datasheet

ADV7300A/ADV7301A

Part	Datasheet
ADV7301AKST	ADV7301AKST (pdf)

PDF Datasheet Preview
Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV 12-Bit DACs ADV7300A/ADV7301A FEATURES High Definition Input Formats YCrCb Compliant to SMPTE293M 525 p , ITU-R.BT1358 625 p , SMPTE274M 1080 i , SMPTE296M 720 p , and Any Other High Definition Standard Using Async Timing Mode CGMS-A 525 p Standard Definition Input Formats CCIR-656 4:2:2 8-/10-Bit Parallel Input CCIR-601 4:2:2 16-/20-Bit Parallel Input Standard Definition Output Formats Composite NTSC M, N; PAL M, N, B, D, G, H, I, PAL-60 SMPTE170M NTSC Compatible Composite Video ITU-R.BT470 PAL Compatible Composite Video S-Video Y/C EuroScart RGB Component YUV Betacam, MII, SMPTE/EBU N10 Macrovision Rev CGMS/WSS Closed Captioning GENERAL FEATURES Simultaneous SD and HD Inputs and Outputs Oversampling 108 MHz/148.5 MHz On-Board Voltage Reference 6 NSV Precision Video 12-Bit DACs 2-Wire Serial MPU Interface Dual I/O Supply V/3.3 V Operation Analog and Digital Supply V On-Board PLL 64-LQFP Package Lead-Free Product APPLICATIONS High End DVD Players SD/Program Scan/HDTV Display Devices SD/Program Scan/HDTV Set-Top Boxes SD/HDTV Studio Equipment SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM S_HSYNC S_VSYNC S_BLANK P_HSYNC P_VSYNC P_BLANK CLKIN_A CLKIN_B STANDARD DEFINITION CONTROL BLOCK COLOR CONTROL BRIGHTNESS GAMMA PROGRAMMABLE FILTERS SD TEST PATTERN PROGRAMMABLE RGB MATRIX D E M U X TIMING GENERATOR HIGH DEFINITION CONTROL BLOCK HD TEST PATTERN COLOR CONTROL ADAPTIVE FILTER CTRL SHARPNESS FILTER ADV7300A/ ADV7301A 12-BIT DAC O 12-BIT 12-BIT DAC P 12-BIT N 12-BIT 12-BIT DAC I2C INTERFACE GENERAL DESCRIPTION The ADV7300A/ADV7301A is a high speed, digital-to-analog encoder on a single monolithic chip. It includes six high speed video D/A converters with TTL compatible inputs. The ADV7300A/ADV7301A has three separate 10-bit wide input ports that accept data in high definition and/or standard definition video format. For all standards, external horizontal, vertical, and blanking signals, or EAV/SAV timing codes, control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signals. NSV Noise Shaped Video is a trademark of Analog Devices, Inc. *ADV7300A Only Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel 781/329-4700 Fax 781/326-8703 Analog Devices, Inc., 2002 ORDERING GUIDE Model ADV7300AKST ADV7301AKST Package Description Plastic Quad Flatpack Plastic Quad Flatpack Package Option ST-64B ST-64B CAUTION ESD electrostatic discharge sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7300A/ADV7301A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATION GND_IO CLKN_B S9 S8 S7 S6 S5 DGND VDD S4 S3 S2 S1 S0 S_HSYNC S_VSYNC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDD_IO 1 Y0 2 Y1 3 Y2 4 Y3 5 Y4 6 Y5 7 Y6 8 Y7 9 VDD 10 DGND 11 Y8 12 Y9 13 C0 14 C1 15 C2 16 PIN 1 IDENTIFIER ADV7300A/ADV7301A TOP VIEW Not to Scale 48 S_BLANK 47 RSET1 46 VREF 45 COMP1 44 DAC A 43 DAC B 42 DAC C 41 VAA 40 AGND 39 DAC D 38 DAC E 37 DAC F 36 COMP2 35 RSET2 34 EXT_LF 33 RESET 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C3 C4 I2C ALSB SDA SCLK P_HSYNC P_VSYNC P_BLANK C5 C6 C7 C8 C9 RTC_SCR_TR CLKIN_A Pin No. 1 12, 13 10, 56 11, 57 Mnemonic VDD_IO VDD DGND PIN FUNCTION DESCRIPTIONS Input/Output P I Function Power Supply for Digital Inputs and Outputs 10-Bit Progressive Scan/HDTV Input Port for Y Data. The LSBs are set up on Pins Y0 and Y1. In Default Mode, the input on this port is output on DAC D. Digital Power Supply Digital Ground ADV7300A/ADV7301A Pin No. 19 20 21 22 23 24 25 31 32 33 34 35, 47 36, 45 37 38 39 40 41 42 43 44 46 48 49 50 Mnemonic Input/Output I ALSB SCLK P_HSYNC P_VSYNC P_BLANK RTC_SCR_TR I CLKIN_A RESET

PDF Datasheet Preview

Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV 12-Bit DACs

ADV7300A/ADV7301A

FEATURES High Definition Input Formats

YCrCb Compliant to SMPTE293M 525 p , ITU-R.BT1358 625 p , SMPTE274M 1080 i , SMPTE296M 720 p , and Any Other High Definition Standard Using Async Timing Mode

CGMS-A 525 p Standard Definition Input Formats

CCIR-656 4:2:2 8-/10-Bit Parallel Input CCIR-601 4:2:2 16-/20-Bit Parallel Input Standard Definition Output Formats Composite NTSC M, N;

PAL M, N, B, D, G, H, I, PAL-60 SMPTE170M NTSC Compatible Composite Video ITU-R.BT470 PAL Compatible Composite Video S-Video Y/C EuroScart RGB Component YUV Betacam, MII, SMPTE/EBU N10 Macrovision Rev

CGMS/WSS Closed Captioning

GENERAL FEATURES Simultaneous SD and HD Inputs and Outputs Oversampling 108 MHz/148.5 MHz On-Board Voltage Reference 6 NSV Precision Video 12-Bit DACs 2-Wire Serial MPU Interface Dual I/O Supply V/3.3 V Operation Analog and Digital Supply V On-Board PLL 64-LQFP Package Lead-Free Product

APPLICATIONS High End DVD Players SD/Program Scan/HDTV Display Devices SD/Program Scan/HDTV Set-Top Boxes SD/HDTV Studio Equipment

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

S_HSYNC S_VSYNC S_BLANK P_HSYNC P_VSYNC P_BLANK CLKIN_A CLKIN_B

STANDARD DEFINITION CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

GAMMA

PROGRAMMABLE FILTERS

SD TEST PATTERN

PROGRAMMABLE RGB MATRIX

D E M U X

TIMING GENERATOR

HIGH DEFINITION CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL ADAPTIVE FILTER CTRL

SHARPNESS FILTER

ADV7300A/ ADV7301A
12-BIT DAC

O 12-BIT
12-BIT DAC

P 12-BIT

N 12-BIT
12-BIT DAC

I2C INTERFACE

GENERAL DESCRIPTION The ADV7300A/ADV7301A is a high speed, digital-to-analog encoder on a single monolithic chip. It includes six high speed video D/A converters with TTL compatible inputs.

The ADV7300A/ADV7301A has three separate 10-bit wide input ports that accept data in high definition and/or standard definition video format. For all standards, external horizontal, vertical, and blanking signals, or EAV/SAV timing codes, control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signals.

NSV Noise Shaped Video is a trademark of Analog Devices, Inc. *ADV7300A Only

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel 781/329-4700

Fax 781/326-8703

Analog Devices, Inc., 2002
ORDERING GUIDE

Model

ADV7300AKST ADV7301AKST

Package Description

Plastic Quad Flatpack Plastic Quad Flatpack

Package Option

ST-64B ST-64B

CAUTION ESD electrostatic discharge sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7300A/ADV7301A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATION

GND_IO CLKN_B S9 S8 S7 S6 S5 DGND VDD S4 S3 S2 S1 S0 S_HSYNC S_VSYNC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VDD_IO 1 Y0 2 Y1 3 Y2 4 Y3 5 Y4 6 Y5 7 Y6 8 Y7 9

VDD 10 DGND 11

Y8 12 Y9 13 C0 14 C1 15 C2 16

PIN 1 IDENTIFIER

ADV7300A/ADV7301A

TOP VIEW Not to Scale
48 S_BLANK 47 RSET1 46 VREF 45 COMP1 44 DAC A 43 DAC B 42 DAC C 41 VAA 40 AGND 39 DAC D 38 DAC E 37 DAC F 36 COMP2 35 RSET2 34 EXT_LF 33 RESET
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

C3 C4 I2C ALSB SDA SCLK P_HSYNC P_VSYNC P_BLANK C5 C6 C7 C8 C9 RTC_SCR_TR CLKIN_A

Pin No. 1 12, 13
10, 56 11, 57

Mnemonic VDD_IO

VDD DGND

PIN FUNCTION DESCRIPTIONS

Input/Output P I

Function

Power Supply for Digital Inputs and Outputs 10-Bit Progressive Scan/HDTV Input Port for Y Data. The LSBs are set up on Pins Y0 and Y1. In Default Mode, the input on this port is output on DAC D. Digital Power Supply Digital Ground

ADV7300A/ADV7301A

Pin No.
19 20 21 22 23 24 25 31 32 33 34 35, 47 36, 45 37 38 39 40 41 42 43 44 46 48 49 50

Mnemonic

Input/Output I

ALSB

SCLK

P_HSYNC

P_VSYNC

P_BLANK

RTC_SCR_TR I

CLKIN_A

RESET

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Datasheet ID: ADV7301AKST 517877