MPC9993FA
MPC9993FA Datasheet
The MPC9993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs.
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MPC9993FA |
MPC9993FA (pdf) |
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| Freescale Semiconductor Technical Data Intelligent Dynamic Clock Switch IDCS PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. • Fully Integrated PLL • Intelligent Dynamic Clock Switch • LVPECL Clock Outputs • LVCMOS Control I/O • V Operation • 32-Lead LQFP Packaging • 32-Lead Pb-Free Package Available Functional Description The MPC9993 Intelligent Dynamic Clock Switch IDCS circuit continuously monitors both input CLK signals. Upon detection of a failure CLK stuck HIGH or LOW for at least 1 period , the INP_BAD for that CLK will be latched H . If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. See Application Information section . MPC9993 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 PLL_En Clk_Selected Inp1bad Inp0bad Man_Override Alarm_Reset Dynamic Switch Logic Sel_Clk CLK0 CLK0 CLK1 CLK1 ÷16 Ext_FB Ext_FB 800 1600 MHz Figure Block Diagram Freescale Semiconductor, Inc., All rights reserved. Qa1 Qa0 VCC VCC_PLL Man_Override PLL_EN 24 23 22 21 20 19 18 17 MPC9993 12345678 VCC Inp0bad Inp1bad Clk_Selected GND Ext_FB Ext_FB GND CLK1 CLK1 Sel_Clk CLK0 CLK0 Alarm_Reset Figure 32-Lead Pinout Top View Table Pin Descriptions |
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