MPC941FA

MPC941FA Datasheet

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Part	Datasheet
MPC941FA	MPC941FA (pdf)

Related Parts	Information
MPC941AE	MPC941AE

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Freescale Semiconductor, Inc... MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order this document by MPC941/D Low Voltage 1:27 Clock Distribution Chip MPC941 The MPC941 is a 1:27 low voltage clock distribution chip. The device features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 27 outputs are LVCMOS compatible and feature the drive strength to drive series or parallel terminated transmission lines. With skews of 250ps, the MPC941 is ideal as a clock distribution chip for the most demanding of synchronous systems. For a similar product with a smaller number of outputs, please consult the MPC940 data sheet. LOW VOLTAGE 3.3V/2.5V 1:27 CLOCK DISTRIBUTION CHIP • LVPECL or LVCMOS Clock Input • 250ps Maximum Skew • Drives Up to 54 Independent Clock Lines • Maximum Output Frequency of 250MHz • High Impedance Output Enable • LQFP Packaging • 3.3V or 2.5V VCC Supply Voltage With a low output impedance, in both the HIGH and LOW logic states, the output buffers of the MPC941 are ideal for driving series terminated transmission lines. More specifically, each of the 27 MPC941 outputs can drive two series terminated transmission lines. With this capability, the MPC941 has an effective fanout of With this level of fanout, the MPC941 provides enough copies of low skew clocks for most high performance synchronous systems. FA SUFFIX LQFP PACKAGE CASE The differential LVPECL inputs of the MPC941 allow the device to interface directly with an LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used as a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. The MPC941 is fully 3.3V and 2.5V compatible. The LQFP package was chosen to optimize performance, board space and cost of the device. The LQFP has a 7x7mm body size. 02/01 Motorola, Inc. 2001 MPC941 Freescale Semiconductor, Inc. PECL_CLK LVCMOS_CLK LVCMOS_CLK_Sel pulldown LOGIC DIAGRAM 0 1 OE pulldown Q0 25 Pinout QFP Top View 36 35 34 33 32 31 30 29 28 27 26 25 MPC941 1 2 3 4 5 6 7 8 9 10 11 12 FUNCTION TABLE LVCMOS_CLK_Sel Input PECL_CLK LVCMOS_CLK Freescale Semiconductor, Inc...

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Freescale Semiconductor, Inc...

MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document by MPC941/D

Low Voltage 1:27 Clock Distribution Chip

MPC941

The MPC941 is a 1:27 low voltage clock distribution chip. The device features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 27 outputs are LVCMOS compatible and feature the drive strength to drive series or parallel terminated transmission lines. With skews of 250ps, the MPC941 is ideal as a clock distribution chip for the most demanding of synchronous systems. For a similar product with a smaller number of outputs, please consult the MPC940 data sheet.

LOW VOLTAGE 3.3V/2.5V 1:27 CLOCK

DISTRIBUTION CHIP
• LVPECL or LVCMOS Clock Input
• 250ps Maximum Skew
• Drives Up to 54 Independent Clock Lines
• Maximum Output Frequency of 250MHz
• High Impedance Output Enable
• LQFP Packaging
• 3.3V or 2.5V VCC Supply Voltage

With a low output impedance, in both the HIGH and LOW logic states, the output buffers of the MPC941 are ideal for driving series terminated transmission lines. More specifically, each of the 27 MPC941 outputs can drive two series terminated transmission lines. With this capability, the MPC941 has an effective fanout of With this level of fanout, the MPC941 provides enough copies of low skew clocks for most high performance synchronous systems.

FA SUFFIX LQFP PACKAGE

CASE

The differential LVPECL inputs of the MPC941 allow the device to interface directly with an LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used as a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input.

The MPC941 is fully 3.3V and 2.5V compatible. The LQFP package was chosen to optimize performance, board space and cost of the device. The LQFP has a 7x7mm body size.
02/01

Motorola, Inc. 2001

MPC941

Freescale Semiconductor, Inc.

PECL_CLK LVCMOS_CLK

LVCMOS_CLK_Sel
pulldown

LOGIC DIAGRAM 0 1

OE pulldown

Q0 25

Pinout QFP Top View
36 35 34 33 32 31 30 29 28 27 26 25

MPC941
1 2 3 4 5 6 7 8 9 10 11 12

FUNCTION TABLE

LVCMOS_CLK_Sel

Input

PECL_CLK LVCMOS_CLK

Freescale Semiconductor, Inc...

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Datasheet ID: MPC941FA 635571