MPC555CME

MPC555CME Datasheet

MPC555 / MPC556

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MPC555CME	MPC555CME (pdf)

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MPC555 / MPC556 USER’S MANUAL Copyright 2000 MOTOROLA All Rights Reserved MPC555 / MPC556 USER’S MANUAL Copyright 2000 MOTOROLA All Rights Reserved Paragraph Number TABLE OF CONTENTS Page Number Section 1 OVERVIEW Block Diagram 1-1 MPC555 / MPC556 Features 1-2 RISC MCU Central Processing Unit RCPU 1-2 Four-Bank Memory Controller 1-3 U-Bus System Interface Unit USIU 1-3 Flexible Memory Protection Unit. 1-3 448 Kbytes of CDR MoneT Flash EEPROM Memory CMF 1-3 26 Kbytes of Static RAM. 1-3 General-Purpose I/O Support 1-4 Two Time Processor Units TPU3 1-4 18-Channel Modular I/O System MIOS1 1-4 Two Queued Analog-to-Digital Converter Modules QADC 1-4 Two CAN 2.0B Controller Modules TouCANs 1-5 Queued Serial Multi-Channel Module QSMCM 1-5 MPC555 / MPC556 Address Map 1-5 Section 2 SIGNAL DESCRIPTIONS Packaging and Pinout Descriptions 2-1 Pin Functionality. 2-6 Signal Descriptions 2-12 USIU Pads 2-12 ADDR[8:31]/SGPIOA[8:31]. 2-12 DATA[0:31]/SGPIOD[0:31] 2-13 IRQ[0]/SGPIOC[0] 2-13 IRQ[1]/RSV/SGPIOC[1] 2-13 IRQ[2]/CR/SGPIOC[2]/MTS 2-13 IRQ[3]/KR/RETRY/SGPIOC[3] 2-13 IRQ[4]/AT[2]/SGPIOC[4]. 2-14 IRQ[5]/SGPIOC[5]/MODCK[1] 2-14 IRQ[6:7]/MODCK[2:3]. 2-14 TSIZ[0:1]. 2-14 RD/WR 2-15 BURST 2-15 BDIP 2-15 TS 2-15 TA 2-15 MPC555 / MPC556 USER’S MANUAL MOTOROLA iii Paragraph Number Number TEA. 2-15 RSTCONF/TEXP 2-16 OE 2-16 BI/STS 2-16 CS[0:3] 2-16 WE[0:3]/BE[0:3]/AT[0:3] 2-16 PORESET 2-17 HRESET 2-17 SRESET 2-17 SGPIOC[6]/FRZ/PTR 2-17 SGPIOC[7]/IRQOUT/LWP[0] 2-18 BG/VF[0]/LWP[1] 2-18 BR/VF[1]/IWP[2] 2-18 BB/VF[2]/IWP[3] 2-18 IWP[0:1]/VFLS[0:1]. 2-19 TMS 2-19 TDI/DSDI 2-19 TCK/DSCK 2-19 TDO/DSDO. 2-19 TRST 2-20 XTAL. 2-20 Little-Endian Byte Ordering 3-42 PowerPC Virtual Environment Architecture VEA . 3-42 Atomic Update Primitives 3-42 Effect of Operand Placement on Performance 3-42 Storage Control Instructions 3-42 Instruction Synchronize isync Instruction 3-42 Enforce In-Order Execution of I/O eieio Instruction 3-43 Timebase 3-43 POWERPC Operating Environment Architecture OEA 3-43 Branch Processor Registers 3-43 Machine State Register MSR . 3-43 Branch Processors Instructions 3-43 Fixed-Point Processor 3-43 Special Purpose Registers 3-43 Storage Control Instructions 3-44 Interrupts 3-44 System Reset Interrupt. 3-44 MPC555 / MPC555 USER’S MANUAL MOTOROLA viii Paragraph Number Number Machine Check Interrupt 3-45 Data Storage Interrupt 3-45 Instruction Storage Interrupt 3-46 Alignment Interrupt 3-46 Floating-Point Enabled Exception Type Program Interrupt 3-46 Illegal Instruction Type Program Interrupt 3-46 Privileged Instruction Type Program interrupt 3-46 Floating-Point Unavailable Interrupt 3-47 Trace Interrupt 3-47 Floating-Point Assist Interrupt 3-47 Implementation-Dependent Software Emulation Interrupt 3-48 Implementation-Specific Instruction Storage Protection Error Interrupt 3-49 Implementation-Specific Data Storage Protection Error Interrupt 3-50 Implementation-Specific Debug Interrupts 3-51 Partially Executed Instructions 3-52 Timer Facilities 3-53 Optional Facilities and Instructions 3-53 Section 4 BURST BUFFER Burst Buffer Block Diagram 4-1 Burst Buffer Features 4-2 Instruction VocabularyBased Compression Model Main Principles 4-3 • Facilities for enhanced system performance Programmable big- and little-endian byte ordering Atomic memory references • In-system testability and debugging features • High instruction and data throughput Condition register CR look-ahead operations performed by BPU Branch-folding capability during execution zero-cycle branch execution time Programmable static branch prediction on unresolved conditional branches A pre-fetch queue that can hold up to four instructions, providing look-ahead capability Interlocked pipelines with feed-forwarding that control data dependencies in hardware MPC555 / MPC556 USER’S MANUAL MOTOROLA 3-1 RCPU Block Diagram Figure 3-1 provides a block diagram of the RCPU. RCPU L-DATA FPR HISTORY FPR 32 X 64 LOAD/STORE FLOATING DATA L-ADDR I-DATA I-ADDR INSTRUCTION SEQUENCER INSTRUCTION PRE-FETCH QUEUE LOAD/ STORE INTEGER DATA LOAD/ STORE ADDRESS ALU/ BFU IMUL/ IDIV BRANCH PROCESSOR UNIT GPR HISTORY GPR 32 X 32 NEXT ADDRESS GENERATION CONTROL REGS WRITE BACK BUS 2 SLOTS/CLOCK Figure 3-1 RCPU Block Diagram MPC555 / MPC556 USER’S MANUAL CONTROL BUS SOURCE BUSES 4 SLO TS /C LO CK MOTOROLA 3-2 Instruction Sequencer The instruction sequencer provides centralized control over data flow between execution units and register files. The sequencer implements the basic instruction pipeline, fetches instructions from the memory system, issues them to available execution units, and maintains a state history so it can back the machine up in the event of an exception. The instruction sequencer fetches instructions from the burst buffer controller into the instruction pre-fetch queue. The BPU extracts branch instructions from the pre-fetch queue and uses static branch prediction on unresolved conditional branches to allow the instruction unit to fetch instructions from a predicted target instruction stream while a conditional branch is evaluated. The BPU folds out branch instructions for unconditional branches or conditional branches unaffected by instructions in the execution stage. Instructions issued beyond a predicted branch do not complete execution until the branch is resolved, preserving the programming model of sequential execution. If branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and instructions are issued from the correct path. MPC555 / MPC556 USER’S MANUAL MOTOROLA 3-3 Little-Endian Byte Ordering The load/store unit supports little-endian byte ordering as specified in the UISA. In little-endian mode, if an attempt is made to execute an individual scalar unaligned transfer, as well as a multiple or string instruction, an alignment interrupt is taken. PowerPC Virtual Environment Architecture VEA Atomic Update Primitives Both the lwarx and stwcx instructions are implemented according to the PowerPC architecture requirements. The MPC555 / MPC556 does not provide support for snooping an external bus activity outside the chip. The provision is made to cancel the reservation inside the MPC555 / MPC556 by using the CR_B and KR_B input pins. Effect of Operand Placement on Performance The load/store unit hardware supports all of the PowerPC load/store instructions. An optimal performance is obtained for naturally aligned operands. These accesses result in optimal performance one bus cycle for up to 4 bytes size and good performance two bus cycles for double precision floating-point operands. Unaligned operands are supported in hardware and are broken into a series of aligned transfers. The effect of operand placement on performance is as stated in the VEA, except for the case of 8byte operands. In that case, since the MPC555 / MPC556 uses a 32-bit wide data bus, the performance is good rather than optimal. Storage Control Instructions The MPC555 / MPC556 does not implement cache control instructions icbi, isync, dcbt, dcbi, dcbf, dcbz, dcbst, and dcbtst Instruction Synchronize isync Instruction The isync instruction causes a reflect which waits for all prior instructions to complete and then executes the next sequential instruction. Any instruction after an isync will see all effects of prior instructions. MPC555 / MPC556 USER’S MANUAL MOTOROLA 3-42 Enforce In-Order Execution of I/O eieio Instruction When executing an eieio instruction, the load/store unit will wait until all previous accesses have terminated before issuing cycles associated with load/store instructions following the eieio instruction. Timebase A description of the timebase register may be found in SECTION 6 SYSTEM CONFIGURATION AND PROTECTION and in SECTION 8 CLOCKS AND POWER CONTROL. POWERPC Operating Environment Architecture OEA The MPC555 / MPC556 has an internal memory space that includes memory-mapped control registers and internal memory used by various modules on the chip. This memory is part of the main memory as seen by the MPC555 / MPC556 but cannot be accessed by any external system master. Branch Processor Registers Machine State Register MSR The floating-point exception mode encoding in the MPC555 / MPC556 core is as follows: Table 3-23 Floating-Point Exception Mode Encoding Mode Ignore exceptions Precise The SF bit is reserved set to zero The IP bit initial state after reset is set as programmed by the reset configuration as specified by the USIU specification. Branch Processors Instructions The MPC555 / MPC556 implements all the instructions defined for the branch processor in the UISA in the hardware. Fixed-Point Processor Special Purpose Registers • Unsupported Registers The following registers are not supported by the MPC555 / MPC556 SDR, EAR, IBAT0U, IBAT0L, IBAT1U, IBAT1L, IBAT2U, IBAT2L, IBAT3U, IBAT3L, DBAT0U, DBAT0L, DBAT1U, DBAT1L, DBAT2L, MPC555 / MPC556 USER’S MANUAL MOTOROLA 3-43 DBAT3U, DBAT3L • Added Registers For a list of added special purpose registers, refer to Table 3-2, and Table Storage Control Instructions Storage Control Instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlbsync are not implemented by the MPC555 / MPC556. Interrupts The core implements all storage-associated interrupts as precise interrupts. This means that a load/store instruction is not complete until all possible error indications have been sampled from the load/store bus. This also implies that a store, or a nonspeculative load instruction is not issued to the load/store bus until all previous instructions have completed. In case of a late error, a store cycle or a nonspeculative load cycle can be issued and then aborted. In each interrupt handler, when registers SRR0 and SRR1 are saved, MSRRI can be set to The following paragraphs define the types of OEA interrupts The exception table vector defines the offset value by interrupt type. Refer to Table System Reset Interrupt A system reset interrupt occurs when the IRQ0 pin is asserted and the following registers are set. Register Name Bits Save/Restore Register 0 SRR0 Set to the effective address of the instruction that the processor attempts to execute next if no interrupt conditions are present Data BITS. These bits are read/write data bits that define the value to be driven to the pad in output mode for each implemented I/O pin of the MPIOSM. While in output mode, a read returns the value of the pad. Note that, when little-endian bit ordering is used, bit 0 corresponds to D15 and bit 15 corresponds to D0. NOTE D[0:4] controls the signals MPIO32B[0:4]. These functions are shared on the MPC555 / MPC556 pins VF[0:2]/MPIO32B[0:2] VFLS[0:1]/MPIO32B[3:4] and can be configured as the alternate function VF[0:2] and VFLS[0:1] . See MIOS1 Test and Pin Control Register. MPIOSM Data Direction Register MPIOSMDDR This read/write register defines the data direction for each implemented I/O pin of the MPIOSM. MPIOSMDDR MPIOSM Data Direction Register 0x30 6102 MSB 0 LSB 15 DDR1 DDR10 DDR9 DDR8 DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 RESET: Table 15-27 MPIOSMDDR Bit Descriptions Bit s 0:15 Name Data direction. These bits are read/write data bits that define the data direction status for each implemented I/O pin of the MPIOSM. Note that, when little-endian bit ordering is used, bit 0 corDDR[15:0] responds to D15 and bit 15 corresponds to D0. 0 = Corresponding pin is input. 1 = Corresponding pin is output. MIOS1 Interrupts The MIOS1 and its submodules are capable of generating interrupts to be transmitted to the CPU via the IMB3. Inside the MIOS1, all the information required for requesting and servicing the interrupts are treated in two different blocks: • The interrupt control section ICS MPC555 / MPC556 USER’S MANUAL MOTOROLA 15-31 • The MIOS interrupt request submodules MIRSM . The MIOS interrupt request submodule gathers service request flags from each group of up to 16 submodules and transfers those requests to the MIOS1 interrupt control section ICS . Figure 15-8 shows a block diagram of the interrupt architecture. Submodule 13 Flags Status Register Level n Enable Register IRQ Pend. Register RQSM #0 Request Acknowledge Submodule 2 IRQ Level Register RQSM #1 Submodules 16 to 23 IMB3 Interrupt Control Section MBISM Figure 15-8 MIOS Interrupt Structure MIOS Interrupt Request Submodule MIRSM Each submodule that is capable of generating an interrupt can assert a flag line when an event occurs. In the MIOS1 configuration, there are eighteen flag lines and two MIRSMs are needed. MPC555 / MPC556 USER’S MANUAL MOTOROLA 15-32 Within the MIOS1, each MIRSM includes: • One 16-bit status register for the flags • One 16-bit enable register • One 16-bit IRQ pending register One bit position in each of the above registers is associated with one submodule. Note that if a submodule in a group of 16 cannot generate interrupts, then its corresponding flag bit in the status register is inactive and reads as zero. When an event occurs in a submodule that activates a flag line, the corresponding flag bit in the status register is set. The status register is read/write, but a flag bit can be reset only if it has previously been read as a one. Writing a one to a flag bit has no effect. When the software intends to clear only one flag bit within a status register, the software must write an 16-bit value of all ones except for a zero in the bit position to be cleared. The enable register is initialized by the software to indicate whether each interrupt request is enabled for the level defined in the ICS. Each bit in the IRQ pending register is the result of a logical “AND” between the corresponding bits in the status and in the enable registers. If a flag bit is set and the level enable bit is also set, then the IRQ pending bit is set and the information is transferred to the interrupt control section that is in charge of sending the corresponding level to the CPU. The IRQ pending register is read only. NOTE When the enable bit is not set for a particular submodule, the corresponding status register bit is still set when the corresponding flag is set. This allows the traditional software approach of polling the flag bits to see which ones are set. The status register makes flag polling easy, since up to sixteen flag bits are contained in one register. The submodule number of an interrupting source defines the corresponding MIRSM number and the bit position in the status registers. To find the MIRSM number and bit position of an interrupting source, divide the interrupting submodule number by The integer result of the division gives the MIRSM number. The remainder of the division gives the bit position. Refer to MIOS Interrupt Request Submodule 0 MIRSM0 Registers and to MIOS Interrupt Request Submodule 1 MIRSM1 Registers for details about the registers in the MIRSM. MIOS Interrupt Request Submodule 0 MIRSM0 Registers Table 15-28 shows the registers associated with the MIRSM0 submodule. MPC555 / MPC556 USER’S MANUAL MOTOROLA 15-33 Table 15-28 MIRSM0 Address Map Address Register 0x30 6C00 MIRSM0 Interrupt Status Register MIOS1SR0 See Table 15-29 for bit descriptions. 0x30 6C02 Reserved

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MPC555 / MPC556

USER’S MANUAL

Copyright 2000 MOTOROLA All Rights Reserved

MPC555 / MPC556

USER’S MANUAL

Copyright 2000 MOTOROLA All Rights Reserved

Paragraph Number

TABLE OF CONTENTS

Page Number

Section 1 OVERVIEW

Block Diagram 1-1 MPC555 / MPC556 Features 1-2

RISC MCU Central Processing Unit RCPU 1-2 Four-Bank Memory Controller 1-3 U-Bus System Interface Unit USIU 1-3 Flexible Memory Protection Unit. 1-3 448 Kbytes of CDR MoneT Flash EEPROM Memory CMF 1-3 26 Kbytes of Static RAM. 1-3 General-Purpose I/O Support 1-4 Two Time Processor Units TPU3 1-4 18-Channel Modular I/O System MIOS1 1-4 Two Queued Analog-to-Digital Converter Modules QADC 1-4 Two CAN 2.0B Controller Modules TouCANs 1-5 Queued Serial Multi-Channel Module QSMCM 1-5 MPC555 / MPC556 Address Map 1-5

Section 2 SIGNAL DESCRIPTIONS

Packaging and Pinout Descriptions 2-1 Pin Functionality. 2-6 Signal Descriptions 2-12

USIU Pads 2-12 ADDR[8:31]/SGPIOA[8:31]. 2-12 DATA[0:31]/SGPIOD[0:31] 2-13 IRQ[0]/SGPIOC[0] 2-13 IRQ[1]/RSV/SGPIOC[1] 2-13 IRQ[2]/CR/SGPIOC[2]/MTS 2-13 IRQ[3]/KR/RETRY/SGPIOC[3] 2-13 IRQ[4]/AT[2]/SGPIOC[4]. 2-14 IRQ[5]/SGPIOC[5]/MODCK[1] 2-14 IRQ[6:7]/MODCK[2:3]. 2-14 TSIZ[0:1]. 2-14 RD/WR 2-15 BURST 2-15 BDIP 2-15 TS 2-15 TA 2-15

MPC555 / MPC556 USER’S MANUAL

MOTOROLA iii

Paragraph

Number

Number

TEA. 2-15

RSTCONF/TEXP 2-16

OE 2-16

BI/STS 2-16

CS[0:3] 2-16

WE[0:3]/BE[0:3]/AT[0:3] 2-16

PORESET 2-17

HRESET 2-17

SRESET 2-17

SGPIOC[6]/FRZ/PTR 2-17

SGPIOC[7]/IRQOUT/LWP[0] 2-18

BG/VF[0]/LWP[1] 2-18

BR/VF[1]/IWP[2] 2-18

BB/VF[2]/IWP[3] 2-18

IWP[0:1]/VFLS[0:1]. 2-19

TMS 2-19

TDI/DSDI 2-19

TCK/DSCK 2-19

TDO/DSDO. 2-19

TRST 2-20

XTAL. 2-20
Little-Endian Byte Ordering 3-42

PowerPC Virtual Environment Architecture VEA . 3-42

Atomic Update Primitives 3-42

Effect of Operand Placement on Performance 3-42

Storage Control Instructions 3-42

Instruction Synchronize isync Instruction 3-42

Enforce In-Order Execution of I/O eieio Instruction 3-43

Timebase 3-43

POWERPC Operating Environment Architecture OEA 3-43

Branch Processor Registers 3-43

Machine State Register MSR . 3-43

Branch Processors Instructions 3-43

Fixed-Point Processor 3-43

Special Purpose Registers 3-43

Storage Control Instructions 3-44

Interrupts 3-44

System Reset Interrupt. 3-44

MPC555 / MPC555 USER’S MANUAL

MOTOROLA viii

Paragraph

Number

Number

Machine Check Interrupt 3-45

Data Storage Interrupt 3-45

Instruction Storage Interrupt 3-46

Alignment Interrupt 3-46

Floating-Point Enabled Exception Type Program Interrupt 3-46

Illegal Instruction Type Program Interrupt 3-46

Privileged Instruction Type Program interrupt 3-46

Floating-Point Unavailable Interrupt 3-47

Trace Interrupt 3-47

Floating-Point Assist Interrupt 3-47

Implementation-Dependent Software Emulation Interrupt 3-48

Implementation-Specific Instruction Storage Protection Error Interrupt 3-49

Implementation-Specific Data Storage Protection Error Interrupt 3-50

Implementation-Specific Debug Interrupts 3-51

Partially Executed Instructions 3-52

Timer Facilities 3-53

Optional Facilities and Instructions 3-53

Section 4 BURST BUFFER

Burst Buffer Block Diagram 4-1 Burst Buffer Features 4-2 Instruction VocabularyBased Compression Model Main Principles 4-3
• Facilities for enhanced system performance Programmable big- and little-endian byte ordering Atomic memory references
• In-system testability and debugging features
• High instruction and data throughput

Condition register CR look-ahead operations performed by BPU Branch-folding capability during execution zero-cycle branch execution time Programmable static branch prediction on unresolved conditional branches A pre-fetch queue that can hold up to four instructions, providing look-ahead
capability Interlocked pipelines with feed-forwarding that control data dependencies in
hardware

MPC555 / MPC556 USER’S MANUAL

MOTOROLA 3-1

RCPU Block Diagram Figure 3-1 provides a block diagram of the RCPU.

RCPU

L-DATA

FPR HISTORY

FPR 32 X 64

LOAD/STORE FLOATING DATA

L-ADDR

I-DATA I-ADDR

INSTRUCTION SEQUENCER

INSTRUCTION PRE-FETCH QUEUE

LOAD/ STORE INTEGER DATA

LOAD/ STORE ADDRESS

ALU/ BFU

IMUL/ IDIV

BRANCH PROCESSOR

UNIT

GPR HISTORY

GPR 32 X 32

NEXT ADDRESS GENERATION

CONTROL REGS

WRITE BACK BUS 2 SLOTS/CLOCK

Figure 3-1 RCPU Block Diagram

MPC555 / MPC556

USER’S MANUAL

CONTROL BUS

SOURCE BUSES 4 SLO TS /C LO CK

MOTOROLA 3-2

Instruction Sequencer

The instruction sequencer provides centralized control over data flow between execution units and register files. The sequencer implements the basic instruction pipeline, fetches instructions from the memory system, issues them to available execution units, and maintains a state history so it can back the machine up in the event of an exception.

The instruction sequencer fetches instructions from the burst buffer controller into the instruction pre-fetch queue. The BPU extracts branch instructions from the pre-fetch queue and uses static branch prediction on unresolved conditional branches to allow the instruction unit to fetch instructions from a predicted target instruction stream while a conditional branch is evaluated. The BPU folds out branch instructions for unconditional branches or conditional branches unaffected by instructions in the execution stage.

Instructions issued beyond a predicted branch do not complete execution until the branch is resolved, preserving the programming model of sequential execution. If branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and instructions are issued from the correct path.

MPC555 / MPC556

USER’S MANUAL

MOTOROLA 3-3
Little-Endian Byte Ordering The load/store unit supports little-endian byte ordering as specified in the UISA. In little-endian mode, if an attempt is made to execute an individual scalar unaligned transfer, as well as a multiple or string instruction, an alignment interrupt is taken.

PowerPC Virtual Environment Architecture VEA

Atomic Update Primitives Both the lwarx and stwcx instructions are implemented according to the PowerPC architecture requirements. The MPC555 / MPC556 does not provide support for snooping an external bus activity outside the chip. The provision is made to cancel the reservation inside the MPC555 / MPC556 by using the CR_B and KR_B input pins.

Effect of Operand Placement on Performance The load/store unit hardware supports all of the PowerPC load/store instructions. An optimal performance is obtained for naturally aligned operands. These accesses result in optimal performance one bus cycle for up to 4 bytes size and good performance two bus cycles for double precision floating-point operands. Unaligned operands are supported in hardware and are broken into a series of aligned transfers. The effect of operand placement on performance is as stated in the VEA, except for the case of 8byte operands. In that case, since the MPC555 / MPC556 uses a 32-bit wide data bus, the performance is good rather than optimal.

Storage Control Instructions The MPC555 / MPC556 does not implement cache control instructions icbi, isync, dcbt, dcbi, dcbf, dcbz, dcbst, and dcbtst

Instruction Synchronize isync Instruction The isync instruction causes a reflect which waits for all prior instructions to complete and then executes the next sequential instruction. Any instruction after an isync will see all effects of prior instructions.

MPC555 / MPC556

USER’S MANUAL

MOTOROLA 3-42

Enforce In-Order Execution of I/O eieio Instruction

When executing an eieio instruction, the load/store unit will wait until all previous accesses have terminated before issuing cycles associated with load/store instructions following the eieio instruction.

Timebase

A description of the timebase register may be found in SECTION 6 SYSTEM CONFIGURATION AND PROTECTION and in SECTION 8 CLOCKS AND POWER CONTROL.

POWERPC Operating Environment Architecture OEA

The MPC555 / MPC556 has an internal memory space that includes memory-mapped control registers and internal memory used by various modules on the chip. This memory is part of the main memory as seen by the MPC555 / MPC556 but cannot be accessed by any external system master.

Branch Processor Registers

Machine State Register MSR

The floating-point exception mode encoding in the MPC555 / MPC556 core is as follows:

Table 3-23 Floating-Point Exception Mode Encoding

Mode Ignore exceptions Precise

The SF bit is reserved set to zero

The IP bit initial state after reset is set as programmed by the reset configuration as specified by the USIU specification.

Branch Processors Instructions

The MPC555 / MPC556 implements all the instructions defined for the branch processor in the UISA in the hardware.

Fixed-Point Processor

Special Purpose Registers
• Unsupported Registers The following registers are not supported by the MPC555 / MPC556 SDR, EAR, IBAT0U, IBAT0L, IBAT1U, IBAT1L, IBAT2U, IBAT2L, IBAT3U, IBAT3L, DBAT0U, DBAT0L, DBAT1U, DBAT1L, DBAT2L,

MPC555 / MPC556

USER’S MANUAL

MOTOROLA 3-43

DBAT3U, DBAT3L
• Added Registers For a list of added special purpose registers, refer to Table
3-2, and Table

Storage Control Instructions Storage Control Instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlbsync are not implemented by the MPC555 / MPC556.

Interrupts The core implements all storage-associated interrupts as precise interrupts. This means that a load/store instruction is not complete until all possible error indications have been sampled from the load/store bus. This also implies that a store, or a nonspeculative load instruction is not issued to the load/store bus until all previous instructions have completed. In case of a late error, a store cycle or a nonspeculative load cycle can be issued and then aborted.

In each interrupt handler, when registers SRR0 and SRR1 are saved, MSRRI can be set to

The following paragraphs define the types of OEA interrupts The exception table vector defines the offset value by interrupt type. Refer to Table

System Reset Interrupt A system reset interrupt occurs when the IRQ0 pin is asserted and the following registers are set.

Register Name

Bits

Save/Restore Register 0 SRR0

Set to the effective address of the instruction that the processor attempts to execute next if no interrupt conditions are present
Data BITS. These bits are read/write data bits that define the value to be driven to the pad in output mode for each implemented I/O pin of the MPIOSM. While in output mode, a read returns the value of the pad. Note that, when little-endian bit ordering is used, bit 0 corresponds to D15 and bit 15 corresponds to D0.

NOTE

D[0:4] controls the signals MPIO32B[0:4]. These functions are shared on the MPC555 / MPC556 pins VF[0:2]/MPIO32B[0:2] VFLS[0:1]/MPIO32B[3:4] and can be configured as the alternate function VF[0:2] and VFLS[0:1] . See MIOS1 Test and Pin Control Register.

MPIOSM Data Direction Register MPIOSMDDR

This read/write register defines the data direction for each implemented I/O pin of the MPIOSM.

MPIOSMDDR MPIOSM Data Direction Register
0x30 6102

MSB 0

LSB 15

DDR1 DDR10 DDR9 DDR8 DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 RESET:

Table 15-27 MPIOSMDDR Bit Descriptions

Bit s 0:15

Name
Data direction. These bits are read/write data bits that define the data direction status for each implemented I/O pin of the MPIOSM. Note that, when little-endian bit ordering is used, bit 0 corDDR[15:0] responds to D15 and bit 15 corresponds to D0. 0 = Corresponding pin is input. 1 = Corresponding pin is output.

MIOS1 Interrupts The MIOS1 and its submodules are capable of generating interrupts to be transmitted to the CPU via the IMB3. Inside the MIOS1, all the information required for requesting and servicing the interrupts are treated in two different blocks:
• The interrupt control section ICS

MPC555 / MPC556

USER’S MANUAL

MOTOROLA 15-31
• The MIOS interrupt request submodules MIRSM . The MIOS interrupt request submodule gathers service request flags from each group of up to 16 submodules and transfers those requests to the MIOS1 interrupt control section ICS . Figure 15-8 shows a block diagram of the interrupt architecture.

Submodule 13

Flags Status Register

Level n

Enable Register

IRQ Pend. Register

RQSM #0

Request Acknowledge

Submodule 2 IRQ Level Register

RQSM #1 Submodules 16 to 23

IMB3

Interrupt Control Section MBISM

Figure 15-8 MIOS Interrupt Structure

MIOS Interrupt Request Submodule MIRSM Each submodule that is capable of generating an interrupt can assert a flag line when an event occurs. In the MIOS1 configuration, there are eighteen flag lines and two MIRSMs are needed.

MPC555 / MPC556

USER’S MANUAL

MOTOROLA 15-32

Within the MIOS1, each MIRSM includes:
• One 16-bit status register for the flags
• One 16-bit enable register
• One 16-bit IRQ pending register One bit position in each of the above registers is associated with one submodule. Note that if a submodule in a group of 16 cannot generate interrupts, then its corresponding flag bit in the status register is inactive and reads as zero.

When an event occurs in a submodule that activates a flag line, the corresponding flag bit in the status register is set. The status register is read/write, but a flag bit can be reset only if it has previously been read as a one. Writing a one to a flag bit has no effect. When the software intends to clear only one flag bit within a status register, the software must write an 16-bit value of all ones except for a zero in the bit position to be cleared.

The enable register is initialized by the software to indicate whether each interrupt request is enabled for the level defined in the ICS.

Each bit in the IRQ pending register is the result of a logical “AND” between the corresponding bits in the status and in the enable registers. If a flag bit is set and the level enable bit is also set, then the IRQ pending bit is set and the information is transferred to the interrupt control section that is in charge of sending the corresponding level to the CPU. The IRQ pending register is read only.

NOTE When the enable bit is not set for a particular submodule, the corresponding status register bit is still set when the corresponding flag is set. This allows the traditional software approach of polling the flag bits to see which ones are set. The status register makes flag polling easy, since up to sixteen flag bits are contained in one register.

The submodule number of an interrupting source defines the corresponding MIRSM number and the bit position in the status registers. To find the MIRSM number and bit position of an interrupting source, divide the interrupting submodule number by The integer result of the division gives the MIRSM number. The remainder of the division gives the bit position.

Refer to MIOS Interrupt Request Submodule 0 MIRSM0 Registers and to MIOS Interrupt Request Submodule 1 MIRSM1 Registers for details about the registers in the MIRSM.

MIOS Interrupt Request Submodule 0 MIRSM0 Registers Table 15-28 shows the registers associated with the MIRSM0 submodule.

MPC555 / MPC556

USER’S MANUAL

MOTOROLA 15-33

Table 15-28 MIRSM0 Address Map

Address

Register
0x30 6C00

MIRSM0 Interrupt Status Register MIOS1SR0 See Table 15-29 for bit descriptions.
0x30 6C02 Reserved

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Datasheet ID: MPC555CME 635545