MC145158DW2

MC145158DW2 Datasheet

MC145151-2 MC145152-2 MC145155-2 MC145156-2 MC145157-2 MC145158-2

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MC145158DW2	MC145158DW2 (pdf)

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MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order this document by PLL Frequency Synthesizer Family CMOS The devices described in this document are typically used as loop frequency synthesizers. When combined with an external filter and oscillator, these devices can provide all the remaining functions for a PLL frequency synthesizer operating up to the device’s frequency limit. For higher VCO frequency operation, a down mixer or a prescaler can be used between the VCO and the synthesizer IC. These frequency synthesizer chips can be found in the following and other applications: CATV AM/FM Radios TV Tuning Scanning Receivers Amateur Radio MC145151-2 MC145152-2 MC145155-2 MC145156-2 MC145157-2 MC145158-2 CONTROL LOGIC Freescale Semiconductor, Inc... ÷ P/P + 1 OUTPUT FREQUENCY DEVICE DETAIL SHEETS CONTENTS 2 5 9 12 FAMILY CHARACTERISTICS Maximum Ratings 15 DC Electrical Characteristics 15 AC Electrical Characteristics 17 Timing Requirements 18 Frequency Characteristics 19 Phase Detector/Lock Detector Output Waveforms 19 DESIGN CONSIDERATIONS Loop Filter Design 20 Crystal Oscillator Considerations 21 Prescaling 22 MOMoTtoOroRla,OInLc.A1999 For More Information On This through Go to: Freescale Semiconductor, Inc... MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Parallel-Input PLL Frequency Synthesizer Interfaces with Prescalers The is programmed by 14 data lines for the N counter and three input lines for the R counter. The device features consist of a reference oscillator, divider, detector, and programmable counter. The is an replacement for the power consumption has decreased and ESD and performance have improved. • Operating Temperature Range 40 to 85°C • Low Power Consumption Through Use of CMOS Technology • to V Supply Range • or Reference Oscillator Operation • Lock Detect Signal • ÷ N Counter Output Available • Single Modulus/Parallel Programming • 8 ÷ R Values 8, 128, 256, 512, 1024, 2048, 2410, 8192 • ÷ N Range = 3 to 16383 • “Linearized” Digital Phase Detector Enhances Transfer Function Linearity • Two Error Signal Options or • Chip Complexity 8000 FETs or 2000 Equivalent Gates MC145151-2 P SUFFIX PLASTIC DIP CASE 710 DW SUFFIX SOG PACKAGE CASE 751F ORDERING INFORMATION MC145151P2 Plastic DIP MC145151DW2 SOG Package PIN ASSIGNMENT fin 1 VSS 2 VDD 3 PDout 4 RA0 5 RA1 6 RA2 7 8 9 fV 10 N0 11 N1 12 N2 13 N3 14 28 LD 27 OSCin 26 OSCout 25 N11 24 N10 23 N13 22 N12 21 T/R 20 N9 19 N8 18 N7 17 N6 16 N5 15 N4 MCM1ot4o5ro1la5, More Information On This Product, Go to: MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. BLOCK DIAGRAM OSCout OSCin fin T/R 14 x 8 ROM REFERENCE DECODER ÷ R COUNTER ÷ N COUNTER VDD 14 TRANSMIT OFFSET ADDER N13 N11 N9 N7 N6 N4 N2 N0 LOCK DETECT PHASE DETECTOR PDout PHASE DETECTOR NOTE N0 N13 inputs and inputs RA0, RA1, and RA2 have resistors that are not shown. PIN DESCRIPTIONS INPUT PINS fin Frequency Input Pin 1 Input to the ÷ N portion of the synthesizer. fin is typically derived from loop VCO and is ac coupled into the device. For larger amplitude signals standard CMOS logic levels dc coupling may be used. RA0 RA2 Reference Address Inputs Pins 5, 6, 7 These three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below. resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter data to the zero state. Reference Address Code 0 1 0 1 0 1 0 1 0 1 0 1 Total Divide Value 8 128 256 512 1024 2048 2410 8192 N0 N11 N Counter Programming Inputs Pins 11 20, 22 25 ORDERING INFORMATION MC145152P2 Plastic DIP MC145152DW2 SOG Package PIN ASSIGNMENT fin 1 VSS 2 VDD 3 RA0 4 RA1 5 RA2 6 7 8 MC 9 A5 10 N0 11 N1 12 N2 13 N3 14 28 LD 27 OSCin 26 OSCout 25 A4 24 A3 23 A0 22 A2 21 A1 20 N9 19 N8 18 N7 17 N6 16 N5 15 N4 MOMoTtoOroRla,OInLc.A1995 For More Information On This through Go to: OSCout OSCin Freescale Semiconductor, Inc. BLOCK DIAGRAM 12 x 8 ROM REFERENCE DECODER ÷ R COUNTER CONTROL LOGIC LOCK DETECT PHASE DETECTOR ÷ A COUNTER ÷ N COUNTER Freescale Semiconductor, Inc... A5 A3 A2 A0 N0 N2 N4 N5 N7 N9 NOTE N0 N9, A0 A5, and RA0 RA2 have resistors that are not shown. PIN DESCRIPTIONS INPUT PINS fin Frequency Input Pin 1 Input to the positive edge triggered ÷ N and ÷ A counters. fin is typically derived from a prescaler and is ac coupled into the device. For larger amplitude signals standard CMOS logic levels dc coupling may be used. RA0, RA1, RA2 Reference Address Inputs Pins 4, 5, 6 These three inputs establish a code defining one of eight possible divide values for the total reference divider. The total reference divide values are as follows: Reference Address Code Total Divide Value 8 64 128 256 512 1024 1160 2048 N0 N9 N Counter Programming Inputs Pins 11 20 The N inputs provide the data that is preset into the ÷ N counter when it reaches the count of N0 is the least significant digit and N9 is the most significant. resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter data to the zero state. A0 A5 A Counter Programming Inputs Pins 23, 21, 22, 24, 25, 10 The A inputs define the number of clock cycles of fin that require a logic 0 on the MC output see Prescaling section . The A inputs all have internal resistors that ensure that inputs left open will remain at a logic OSCin, OSCout Reference Oscillator Input/Output Pins 27, 26 These pins form an reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to ground and OSCout to ground. OSCin may also serve as the input for an reference signal. This signal is typically ac coupled to OSCin, but for larger amplitude signals standard CMOS logic levels dc coupling may also be used. In the external reference mode, no connection is required to OSCout. ORDERING INFORMATION MC145157P2 Plastic DIP MC145157DW2 SOG Package PIN ASSIGNMENT OSCin 1 OSCout 2 fV 3 VDD 4 PDout 5 VSS 6 fin 8 16 15 14 REFout 13 fR 12 S/Rout 11 ENB 10 DATA 9 CLK Freescale Semiconductor, Inc... MOMoTtoOroRla,OInLc.A1995 For More Information On This through Go to: Freescale Semiconductor, Inc. BLOCK DIAGRAM Freescale Semiconductor, Inc... CONTROL LSB MSB OSCin OSCout REFout SHIFT REGISTER 14 REFERENCE COUNTER LATCH 14 ÷ R COUNTER LOCK DETECT PHASE DETECTOR PDout DATA CLK CONTROL ÷ N COUNTER ÷ N COUNTER LATCH 14 SHIFT REGISTER PHASE DETECTOR S/Rout PIN DESCRIPTIONS INPUT PINS fin Frequency Input Pin 8 Input frequency from VCO output. A rising edge signal on this input decrements the ÷ N counter. This input has an inverter biased in the linear region to allow use with ac coupled signals as low as 500 mV For larger amplitude signals standard CMOS logic levels , dc coupling may be used. CLK, DATA Shift Clock, Serial Data Inputs Pins 9, 10 Each transition of the clock shifts one bit of data into the shift registers. The last data bit entered determines which counter storage latch is activated a logic 1 selects the reference counter latch and a logic 0 selects the ÷ N counter latch. The entry format is as follows: FIRST DATA BIT INTO SHIFT REGISTER ENB Latch Enable Input Pin 11 A logic high on this pin latches the data from the shift register into the reference divider or ÷ N latches depending on the control bit. The reference divider latches are activated if the control bit is at a logic high and the ÷ N latches are activated ORDERING INFORMATION MC145158P2 Plastic DIP MC145158DW2 SOG Package PIN ASSIGNMENT OSCin 1 OSCout 2 fV 3 VDD 4 PDout 5 VSS 6 fin 8 16 15 14 REFout 13 fR 12 MC 11 ENB 10 DATA 9 CLK Freescale Semiconductor, Inc... MCM1ot4o5ro1la5, More Information On This Product, Go to: MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. BLOCK DIAGRAM OSCin OSCout REFout DATA CLK CONTROL SHIFT REGISTER 14 REFERENCE COUNTER LATCH 14 ÷ R COUNTER CONTROL LOGIC COUNTER ÷ A COUNTER LATCH COUNTER ÷ N COUNTER LATCH LOCK DETECT PHASE DETECTOR PDout PHASE DETECTOR CONTROL LSB PIN DESCRIPTIONS INPUT PINS fin Frequency Input Pin 8 Input frequency from VCO output. A rising edge signal on this input decrements the ÷ A and ÷ N counters. This input has an inverter biased in the linear region to allow use with ac coupled signals as low as 500 mV For larger amplitude signals standard CMOS logic levels , dc coupling may be used. CLK, DATA Shift Clock, Serial Data Inputs Pins 9, 10 Each transition of the CLK shifts one bit of data into the shift registers. The last data bit entered determines which counter storage latch is activated a logic 1 selects the reference counter latch and a logic 0 selects the ÷ A, ÷ N counter latch. The data entry format is as follows: FIRST DATA BIT INTO SHIFT REGISTER

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MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document by

PLL Frequency Synthesizer Family

CMOS

The devices described in this document are typically used as loop frequency synthesizers. When combined with an external filter and oscillator, these devices can provide all the remaining functions for a PLL frequency synthesizer operating up to the device’s frequency limit. For higher VCO frequency operation, a down mixer or a prescaler can be used between the VCO and the synthesizer IC.

These frequency synthesizer chips can be found in the following and other applications:

CATV AM/FM Radios

TV Tuning Scanning Receivers Amateur Radio

MC145151-2 MC145152-2 MC145155-2 MC145156-2 MC145157-2 MC145158-2

CONTROL LOGIC

Freescale Semiconductor, Inc...
÷ P/P + 1

OUTPUT FREQUENCY

DEVICE DETAIL SHEETS

CONTENTS
2 5 9 12

FAMILY CHARACTERISTICS

Maximum Ratings 15 DC Electrical Characteristics 15 AC Electrical Characteristics 17 Timing Requirements 18 Frequency Characteristics 19 Phase Detector/Lock Detector Output Waveforms 19

DESIGN CONSIDERATIONS

Loop Filter Design 20 Crystal Oscillator Considerations 21 Prescaling 22

MOMoTtoOroRla,OInLc.A1999

For More Information On This through

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Freescale Semiconductor, Inc...

MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Parallel-Input PLL Frequency Synthesizer

Interfaces with Prescalers

The is programmed by 14 data lines for the N counter and three input lines for the R counter. The device features consist of a reference oscillator, divider, detector, and programmable counter.

The is an replacement for the power consumption has decreased and ESD and performance have improved.
• Operating Temperature Range 40 to 85°C
• Low Power Consumption Through Use of CMOS Technology
• to V Supply Range
• or Reference Oscillator Operation
• Lock Detect Signal
• ÷ N Counter Output Available
• Single Modulus/Parallel Programming
• 8 ÷ R Values 8, 128, 256, 512, 1024, 2048, 2410, 8192
• ÷ N Range = 3 to 16383
• “Linearized” Digital Phase Detector Enhances Transfer Function Linearity
• Two Error Signal Options or
• Chip Complexity 8000 FETs or 2000 Equivalent Gates

MC145151-2

P SUFFIX PLASTIC DIP

CASE 710

DW SUFFIX SOG PACKAGE

CASE 751F
ORDERING INFORMATION

MC145151P2 Plastic DIP MC145151DW2 SOG Package

PIN ASSIGNMENT
fin 1 VSS 2 VDD 3 PDout 4 RA0 5 RA1 6 RA2 7
8 9 fV 10 N0 11 N1 12

N2 13 N3 14
28 LD 27 OSCin 26 OSCout 25 N11 24 N10 23 N13 22 N12 21 T/R 20 N9 19 N8 18 N7 17 N6 16 N5 15 N4

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MOTOROLA

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Freescale Semiconductor, Inc.

BLOCK DIAGRAM

OSCout OSCin
fin T/R
14 x 8 ROM REFERENCE DECODER
÷ R COUNTER
÷ N COUNTER

VDD 14

TRANSMIT OFFSET ADDER

N13 N11 N9 N7 N6 N4 N2 N0

LOCK

DETECT

PHASE DETECTOR

PDout

PHASE

DETECTOR

NOTE N0 N13 inputs and inputs RA0, RA1, and RA2 have resistors that are not shown.

PIN DESCRIPTIONS

INPUT PINS
fin Frequency Input Pin 1

Input to the ÷ N portion of the synthesizer. fin is typically derived from loop VCO and is ac coupled into the device. For larger amplitude signals standard CMOS logic levels dc coupling may be used.

RA0 RA2 Reference Address Inputs Pins 5, 6, 7

These three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below.
resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter data to the zero state.

Reference Address Code
0 1 0 1
0 1 0 1 0 1 0 1

Total Divide Value
8 128 256 512 1024 2048 2410 8192

N0 N11 N Counter Programming Inputs Pins 11 20, 22 25
ORDERING INFORMATION

MC145152P2 Plastic DIP MC145152DW2 SOG Package

PIN ASSIGNMENT
fin 1 VSS 2 VDD 3 RA0 4 RA1 5 RA2 6
7 8 MC 9 A5 10 N0 11 N1 12 N2 13 N3 14
28 LD 27 OSCin 26 OSCout 25 A4 24 A3 23 A0 22 A2 21 A1 20 N9 19 N8 18 N7 17 N6 16 N5 15 N4

MOMoTtoOroRla,OInLc.A1995

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OSCout OSCin

Freescale Semiconductor, Inc.

BLOCK DIAGRAM
12 x 8 ROM REFERENCE DECODER
÷ R COUNTER

CONTROL LOGIC

LOCK

DETECT

PHASE

DETECTOR
÷ A COUNTER
÷ N COUNTER

Freescale Semiconductor, Inc...

A5 A3 A2 A0

N0 N2 N4 N5 N7 N9

NOTE N0 N9, A0 A5, and RA0 RA2 have resistors that are not shown.

PIN DESCRIPTIONS

INPUT PINS
fin Frequency Input Pin 1

Input to the positive edge triggered ÷ N and ÷ A counters. fin is typically derived from a prescaler and is ac coupled into the device. For larger amplitude signals standard CMOS logic levels dc coupling may be used.

RA0, RA1, RA2 Reference Address Inputs Pins 4, 5, 6

These three inputs establish a code defining one of eight possible divide values for the total reference divider. The total reference divide values are as follows:

Reference Address Code

Total Divide Value
8 64 128 256 512 1024 1160 2048

N0 N9 N Counter Programming Inputs Pins 11 20

The N inputs provide the data that is preset into the ÷ N counter when it reaches the count of N0 is the least significant digit and N9 is the most significant. resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter data to the zero state.

A0 A5 A Counter Programming Inputs Pins 23, 21, 22, 24, 25, 10

The A inputs define the number of clock cycles of fin that require a logic 0 on the MC output see

Prescaling section . The A inputs all have internal resistors that ensure that inputs left open will remain at a logic

OSCin, OSCout Reference Oscillator Input/Output Pins 27, 26

These pins form an reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to ground and OSCout to ground. OSCin may also serve as the input for an reference signal. This signal is typically ac coupled to OSCin, but for larger amplitude signals standard CMOS logic levels dc coupling may also be used. In the external reference mode, no connection is required to OSCout.
ORDERING INFORMATION

MC145157P2 Plastic DIP MC145157DW2 SOG Package

PIN ASSIGNMENT

OSCin 1 OSCout 2
fV 3 VDD 4 PDout 5 VSS 6
fin 8
16 15 14 REFout 13 fR 12 S/Rout 11 ENB
10 DATA
9 CLK

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BLOCK DIAGRAM

Freescale Semiconductor, Inc...

CONTROL LSB MSB

OSCin OSCout REFout

SHIFT REGISTER 14

REFERENCE COUNTER LATCH 14
÷ R COUNTER

LOCK DETECT

PHASE DETECTOR

PDout

DATA CLK

CONTROL
÷ N COUNTER
÷ N COUNTER LATCH
14 SHIFT REGISTER

PHASE

DETECTOR

S/Rout

PIN DESCRIPTIONS

INPUT PINS
fin Frequency Input Pin 8

Input frequency from VCO output. A rising edge signal on this input decrements the ÷ N counter. This input has an inverter biased in the linear region to allow use with ac coupled signals as low as 500 mV For larger amplitude signals standard CMOS logic levels , dc coupling may be used.

CLK, DATA Shift Clock, Serial Data Inputs Pins 9, 10

Each transition of the clock shifts one bit of data into the shift registers. The last data bit entered determines which counter storage latch is activated a logic 1 selects the reference counter latch and a logic 0 selects the ÷ N counter latch. The entry format is as follows:

FIRST DATA BIT INTO SHIFT REGISTER

ENB Latch Enable Input Pin 11

A logic high on this pin latches the data from the shift register into the reference divider or ÷ N latches depending on the control bit. The reference divider latches are activated if the control bit is at a logic high and the ÷ N latches are activated
ORDERING INFORMATION

MC145158P2 Plastic DIP MC145158DW2 SOG Package

PIN ASSIGNMENT

OSCin 1 OSCout 2
fV 3 VDD 4 PDout 5 VSS 6
fin 8
16 15 14 REFout 13 fR 12 MC 11 ENB
10 DATA 9 CLK

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MOTOROLA

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

BLOCK DIAGRAM

OSCin OSCout REFout

DATA CLK

CONTROL

SHIFT REGISTER 14

REFERENCE COUNTER LATCH 14
÷ R COUNTER

CONTROL LOGIC

COUNTER
÷ A COUNTER

LATCH

COUNTER
÷ N COUNTER

LATCH

LOCK DETECT

PHASE DETECTOR

PDout

PHASE

DETECTOR

CONTROL LSB

PIN DESCRIPTIONS

INPUT PINS
fin Frequency Input Pin 8

Input frequency from VCO output. A rising edge signal on this input decrements the ÷ A and ÷ N counters. This input has an inverter biased in the linear region to allow use with ac coupled signals as low as 500 mV For larger amplitude signals standard CMOS logic levels , dc coupling may be used.

CLK, DATA Shift Clock, Serial Data Inputs Pins 9, 10

Each transition of the CLK shifts one bit of data into the shift registers. The last data bit entered determines which counter storage latch is activated a logic 1 selects the reference counter latch and a logic 0 selects the ÷ A, ÷ N counter latch. The data entry format is as follows:

FIRST DATA BIT INTO SHIFT REGISTER

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Datasheet ID: MC145158DW2 635479