MC100ES6221TB

MC100ES6221TB Datasheet


MC100ES6221 Rev 5, 04/2005

Part Datasheet
MC100ES6221TB MC100ES6221TB MC100ES6221TB (pdf)
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Freescale Semiconductor Technical Data

Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer

MC100ES6221

The MC100ES6221 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6221 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems.

LOW VOLTAGE DUAL 1:20 DIFFERENTIAL ECL/PECL/HSTL

CLOCK FANOUT BUFFER
• 1:20 differential clock fanout buffer
• 100 ps maximum device skew
• SiGe technology
• Supports DC to 2 GHz operation of clock or data signals
• ECL/PECL compatible differential clock outputs
• ECL/PECL/HSTL compatible differential clock inputs
• Single V, V, V or V supply
• Standard 52 lead LQFP package with exposed pad for enhanced thermal
characteristics
• Supports industrial temperature range
• Pin and function compatible to the MC100EP221
• 52-lead Pb-free Package Available

Functional Description

TB SUFFIX 52-LEAD LQFP PACKAGE

EXPOSED PAD CASE 1336A-01

AE SUFFIX 52-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 1336A-01

The MC100ES6221 is designed for low skew clock distribution systems and supports clock frequencies up to 2 GHz. The device accepts two clock sources. The CLK0 input can be driven by ECL or PECL compatible signals, the CLK1 input accepts HSTL compatible signals. The selected input signal is distributed to 20 identical, differential ECL/PECL outputs. If VBB is connected to the CLK0 or CLK1 input and bypassed to GND by a 10 nF capacitor, the MC100ES6221 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output.

In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated.

The MC100ES6221 can be operated from a single V or V supply. As most other ECL compatible devices, the MC100ES6221 supports positive PECL and negative ECL supplies. The MC100ES6221 is pin and function compatible to the MC100EP221.

Freescale Semiconductor, Inc., All rights reserved.

Q6 Q7 Q8 Q9 Q10 Q11 VCC

CLK0
0 VEE

CLK1

CLK_SEL

Q0 Q1 Q2 Q3
• Q16 Q17 Q18 Q19
39 38 37 36 35 34 33 32 31 30 29 28 27

MC100ES6221
1 2 3 4 5 6 7 8 9 10 11 12 13

VCC CLK_SEL CLK0 VBB CLK1 VEE Q19 Q18

Figure MC100ES6221 Logic Diagram

Figure 52-Lead Package Pinout Top View

Table Pin Configuration

Type

Function

CLK0, CLK0

Input

ECL/PECL

Differential reference clock signal input

CLK1, CLK1

Input

HSTL
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Datasheet ID: MC100ES6221TB 635465