MC100ES6254AC
MC100ES6254AC Datasheet
Order Number MC100ES6254/D Rev. 3, 05/2004
| Part | Datasheet |
|---|---|
MC100ES6254AC |
MC100ES6254AC (pdf) |
| Related Parts | Information |
|---|---|
|
MC100ES6254FA |
MC100ES6254FA |
| PDF Datasheet Preview |
|---|
| Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA 2.5/3.3V Differential LVPECL 2x2 Clock Switch and Fanout Buffer MC100ES6254 The Motorola MC100ES6254 is a bipolar monolithic differential 2x2 clock switch and fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6254 supports various applications that require to drive precisely aligned clock signals. The device is capable of driving and switching differential LVPECL signals. Using SiGe technology and a fully differential architecture, the device offers superior digital signal characteristics and very low clock skew error. Target applications for this clock driver are high performance clock/data switching, clock distribution or data loopback in computing, networking and telecommunication systems. V DIFFERENTIAL LVPECL 2x2 CLOCK SWITCH AND FANOUT BUFFER Features • Fully differential architecture from input to all outputs • SiGe technology supports near-zero output skew • Supports DC to 3GHz operation1 of clock or data signals • LVPECL compatible differential clock inputs and outputs • LVCMOS compatible control inputs • Single V or V supply • 50 ps maximum device skew1 • Synchronous output enable eliminating output runt pulse generation and metastability • Standard 32 lead LQFP package • Industrial temperature range FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A Functional Description MC100ES6254 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to GHz. Typical applications for the MC100ES6254 are primary clock distribution, switching and loopback systems of high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed communication systems. Primary purpose of the MC100ES6254 is high-speed clock switching applications. In addition, the MC100ES6254 can be configured as single 1:6 or dual 1:3 LVPECL fanout buffer for clock signals, or as loopback device in highspeed data applications. The MC100ES6254 can be operated from a V or V positive supply without the requirement of a negative supply line. 1 The device is functional up to 3 GHz and characterized up to GHz. Motorola, Inc. 2004 For More Information On This Product, Go to: MC100ES6254/D Freescale Semiconductor, Inc. VCC CLK0 VCC CLK1 SEL0 SEL1 Bank A 0 1 Bank B 0 1 QA0 QA1 QA2 QB0 QB1 QB2 OEA OEB Sync Figure MC100ES6254 Logic Diagram Freescale Semiconductor, Inc... VCC GND OEA CLK0 SEL0 GND VCC QA2 VCC QA1 VCC QA0 24 23 22 21 20 19 18 17 MC100ES6254 12345678 QB2 VCC QB1 VCC QB0 VCC GND SEL1 CLK1 OEB GND VCC Figure 32-Lead Package Pinout Top View For More Information On This Product, |
| More datasheets: MIKROE-2011 | DEM5W1SA191 | MOC211R1M | MOC212R1M | MOC213R1M | MOC211R1VM | MOC212R1VM | MOC213R1VM | MAGX-000035-09000P | MC100ES6254FA |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MC100ES6254AC Datasheet file may be downloaded here without warranties.