MC100ES6226FA
MC100ES6226FA Datasheet
Freescale Semiconductor, Inc. Order Number MC100ES6226/D
| Part | Datasheet |
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MC100ES6226FA |
MC100ES6226FA (pdf) |
| Related Parts | Information |
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MC100ES6226AC |
MC100ES6226AC |
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| Freescale Semiconductor, Inc... MOTOROLA Freescale Semiconductor, Inc. Order Number MC100ES6226/D SEMICONDUCTOR TECHNICAL DATA 2.5/3.3V Differential LVPECL 1:9 Clock Distribution Buffer and Clock Divider MC100ES6226 The Motorola MC100ES6226 is a bipolar monolithic differential clock distribution buffer and clock divider. Designed for most demanding clock distribution systems, the MC100ES6226 supports various applications that require a large number of outputs to drive precisely aligned clock signals. Using SiGe technology and a fully differential architecture, the device offers superior digitial signal characteristics and very low clock skew error. Target applications for this clock driver are high performance clock distribution systems for computing, networking and telecommunication systems. 2.5V/3.3V DIFFERENTIAL LVPECL 1:9 CLOCK DISTRIBUTION BUFFER AND CLOCK DIVIDER Features • Fully differential architecture from input to all outputs • SiGe technology supports near-zero output skew • Selectable 1:1 or 1:2 frequency outputs • LVPECL compatible differential clock inputs and outputs • LVCMOS compatible control inputs • Single 3.3V or 2.5V supply • Max. 35 ps maximum output skew within output bank • Max. 50 ps maximum device skew • Supports DC operation and up to 3 GHz typ. clock signals • Synchronous output enable eliminating output runt pulse generation and metastability • Standard 32 lead LQFP package • Industrial temperature range FA SUFFIX LQFP PACKAGE CASE 873A Functional Description MC100ES6226 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to GHz. Typical applications for the MC100ES6226 are primary clock distribution systems on backplanes of high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed communication systems. The MC100ES6226 can be operated from a 3.3V or 2.5V positive supply without the requirement of a negative supply line. Each of the output banks of three differential clock output pairs may be independently configured to distribute the input frequency or half of the input frequency. The FSEL0 and FSEL1 clock frequency selects are asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the ÷2 outputs. Motorola, Inc. 2001 For More Information On This Product, 1 Go to: MC100ES6226 Freescale Semiconductor, Inc. VCC ÷1 FSEL0 FSEL1 Bank A QA0 QA1 Bank B QB0 QB1 Bank C QC0 QC1 QC2 Sync Figure MC100ES6226 Logic Diagram Freescale Semiconductor, Inc... 24 23 22 21 20 19 18 17 MC100ES6226 12345678 FSEL1 FSEL0 MOTOROLA Figure Package Pinout Top View For More Informa2tion On This Product, Go to: TIMING SOLUTIONS Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. |
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