MC100ES6220TB

MC100ES6220TB Datasheet

MC100ES6220 Rev 4, 04/2005

Part	Datasheet
MC100ES6220TB	MC100ES6220TB (pdf)

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Freescale Semiconductor Technical Data Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer MC100ES6220 The MC100ES6220 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6220 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. LOW VOLTAGE DUAL 1:10 DIFFERENTIAL ECL/PECL CLOCK FANOUT BUFFER • Two independent 1:10 differential clock fanout buffers • 130 ps maximum device skew • SiGe technology • Supports DC to 1 GHz operation of clock or data signals • ECL/PECL compatible differential clock outputs • ECL/PECL compatible differential clock inputs • Single V, V, V or V supply • Standard 52-lead LQFP package with exposed pad for enhanced thermal characteristics • Supports industrial temperature range • Pin and function compatible to the MC100EP220 • 52-lead Pb-free Package Available Functional Description TB SUFFIX 52-LEAD LQFP PACKAGE EXPOSED PAD CASE 1336A-01 AE SUFFIX 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 1336A-01 The MC100ES6220 is designed for low skew clock distribution systems and supports clock frequencies up to 1 GHz. The device consists of two independent clock fanout buffers. The CLKA and CLKB inputs can be driven by ECL or PECL compatible signals. The input signal of each clock buffer is distributed to 10 identical, differential ECL/PECL outputs. If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6220 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6220 can be operated from a single V or V supply. As most other ECL compatible devices, the MC100ES6220 supports positive PECL and negative ECL supplies. The MC100ES6220 is pin and function compatible to the MC100EP220. Freescale Semiconductor, Inc., All rights reserved. Fanout Buffer A CLKA Fanout Buffer B CLKB Figure MC100ES6220 Logic Diagram 39 38 37 36 35 34 33 32 31 30 29 28 27 QA5 41 QA5 42 QA4 43 QA4 44 QA3 45 MC100ES6220 QA3 46 QA2 47 QA2 48 QA1 49 QA1 50 QA0 51 QA0 52 1 2 3 4 5 6 7 8 9 10 11 12 13 CLKB CLKB CLKA

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Freescale Semiconductor Technical Data

Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer

MC100ES6220

The MC100ES6220 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6220 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems.

LOW VOLTAGE DUAL 1:10 DIFFERENTIAL ECL/PECL

CLOCK FANOUT BUFFER
• Two independent 1:10 differential clock fanout buffers
• 130 ps maximum device skew
• SiGe technology
• Supports DC to 1 GHz operation of clock or data signals
• ECL/PECL compatible differential clock outputs
• ECL/PECL compatible differential clock inputs
• Single V, V, V or V supply
• Standard 52-lead LQFP package with exposed pad for enhanced thermal
characteristics
• Supports industrial temperature range
• Pin and function compatible to the MC100EP220
• 52-lead Pb-free Package Available

Functional Description

TB SUFFIX 52-LEAD LQFP PACKAGE

EXPOSED PAD CASE 1336A-01

AE SUFFIX 52-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 1336A-01

The MC100ES6220 is designed for low skew clock distribution systems and supports clock frequencies up to 1 GHz. The device consists of two independent clock fanout buffers. The CLKA and CLKB inputs can be driven by ECL or PECL compatible signals. The input signal of each clock buffer is distributed to 10 identical, differential ECL/PECL outputs. If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6220 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output.

In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated.

The MC100ES6220 can be operated from a single V or V supply. As most other ECL compatible devices, the MC100ES6220 supports positive PECL and negative ECL supplies. The MC100ES6220 is pin and function compatible to the MC100EP220.

Freescale Semiconductor, Inc., All rights reserved.

Fanout Buffer A

CLKA

Fanout Buffer B

CLKB

Figure MC100ES6220 Logic Diagram
39 38 37 36 35 34 33 32 31 30 29 28 27

QA5 41

QA5 42

QA4 43

QA4 44

QA3 45

MC100ES6220

QA3 46

QA2 47

QA2 48

QA1 49

QA1 50

QA0 51

QA0 52
1 2 3 4 5 6 7 8 9 10 11 12 13

CLKB

CLKB

CLKA

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Datasheet ID: MC100ES6220TB 635464