ICE40HX640-VQ100

ICE40HX640-VQ100 Datasheet

iCE40 HX-Series Ultra Low-Power mobileFPGA Family

Part	Datasheet
ICE40HX640-VQ100	ICE40HX640-VQ100 (pdf)

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iCE40 HX-Series Ultra Low-Power mobileFPGA Family March 30, 2012 Data Sheet HX-Series - Tablet targeted series optimized for high performance Low cost package offerings Figure 1 iCE40 HX-Series Family Architectural Features Programmable 200 µA at f =0 kHz Logic Block PLB Typical 80% faster than iCE65 Tablet resolution HD video and imaging I/O Bank 0 8 Logic Cells = Programmable Logic Block Proven, high-volume 40 nm, low-power CMOS technology Programmable Interconnect I/O Bank 1 Programmable Interconnect 4Kbit RAM 4Kbit RAM Programmable Interconnect Integrated Phase-Locked Loop PLL I/O Bank 3 Clock multiplication/division for display, SerDes, and memory interface applications Up to 533 MHz PLL Output Reprogrammable from a variety of methods and sources Flexible programmable logic and programmable interconnect fabric JTAG 8K look-up tables LUT4 and flip-flops NVCM Low-power logic and interconnect Complete iCEcube development system and support VHDL and Verilog logic synthesis Place and route software Design and IP core libraries I/O Bank 2 SPI Config Phase-Locked Carry logic Loop Four-input Nonvolatile Configuration Memory NVCM Ordering Information Figure 2 describes the iCE40HX ordering codes for all packaged components. See the separate DiePlus data sheets when ordering die-based products. See the separate iCE40 Pinout Excel files for package and pinout specifications. Figure 2 iCE40HX Ordering Codes packaged, non-die components iCE40HX 8K - CM 225 High Performance Series Package Leads Package Style Logic Cells 640, 1K, 4K, 8K CM = chip-scale ball grid mm pitch CB = chip-scale ball grid mm pitch CT = chip-scale ball grid mm pitch VQ = Very Thin Quad flat pack mm pitch TQ = Thin Quad flat pack mm pitch QN = quad flat no-lead mm pitch iCE40HX8K-CM225 225-ball Chip-Scale BGA Package 7x7 mm footprint, mm pitch Lattice Semiconductor Corporation 30-MAR-2012 2 iCE40 HX-Series Ultra-Low Power mobileFPGA Family Electrical Characteristics All parameter limits are specified under worst-case supply voltage, junction temperature, and processing conditions. Absolute Maximum Ratings Stresses beyond those listed under Table 2 may cause permanent damage to the device. These are stress ratings only functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied. Exposure to absolute maximum conditions for extended periods of time adversely affects device reliability. VCC VPP_2V5 VPP_FAST VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 SPI_VCC VIN_0 VIN_1 VIN_2 VIN_SPI VIN_3 VCCPLL IOUT TJ TSTG Table 2 Absolute Maximum Ratings Minimum Core supply Voltage VPP_2V5 NVCM programming and operating supply Optional fast NVCM programming supply I/O bank supply voltage I/O Banks 0, 1, 2 and 3 plus SPI interface Maximum Voltage applied to PIO pin within a specific I/O bank I/O Banks 0, 1, 2 and 3 plus SPI interface Analog voltage supply to the Phase Locked Loop PLL DC output current per pin Junction temperature Storage temperature, no bias Units V mA °C °C Recommended Operating Conditions Table 3 Recommended Operating Conditions VCC VPP_2V51 VPP_FAST2 SPI_VCC VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 SPI_VCC VCCPLL3 TA TPROG Core supply voltage High Performance, low-power VPP_2V5 NVCM Release from Power-on Reset programming and operating Configure from NVCM supply NVCM programming Optional fast NVCM programming supply

PDF Datasheet Preview

iCE40 HX-Series Ultra Low-Power mobileFPGA Family

March 30, 2012

Data Sheet

HX-Series - Tablet targeted series
optimized for high performance

Low cost package offerings

Figure 1 iCE40 HX-Series Family Architectural Features

Programmable
200 µA at f =0 kHz

Logic Block PLB

Typical
80% faster than iCE65 Tablet resolution HD video and imaging

I/O Bank 0
8 Logic Cells = Programmable Logic Block

Proven, high-volume 40 nm, low-power

CMOS technology

Programmable Interconnect

I/O Bank 1

Programmable Interconnect
4Kbit RAM 4Kbit RAM

Programmable Interconnect

Integrated Phase-Locked Loop PLL

I/O Bank 3

Clock multiplication/division for display, SerDes, and memory interface applications

Up to 533 MHz PLL Output

Reprogrammable from a variety of
methods and sources

Flexible programmable logic and
programmable interconnect fabric

JTAG
8K look-up tables LUT4 and flip-flops

NVCM

Low-power logic and interconnect

Complete iCEcube development system
and support VHDL and Verilog logic synthesis Place and route software Design and IP core libraries

I/O Bank 2

SPI Config

Phase-Locked Carry logic

Loop

Four-input

Nonvolatile Configuration Memory NVCM
Ordering Information Figure 2 describes the iCE40HX ordering codes for all packaged components. See the separate DiePlus data sheets when ordering die-based products. See the separate iCE40 Pinout Excel files for package and pinout specifications. Figure 2 iCE40HX Ordering Codes packaged, non-die components
iCE40HX 8K - CM 225

High Performance Series

Package Leads Package Style

Logic Cells 640, 1K, 4K, 8K

CM = chip-scale ball grid mm pitch CB = chip-scale ball grid mm pitch CT = chip-scale ball grid mm pitch VQ = Very Thin Quad flat pack mm pitch TQ = Thin Quad flat pack mm pitch QN = quad flat no-lead mm pitch
iCE40HX8K-CM225 225-ball Chip-Scale BGA Package 7x7 mm footprint, mm pitch

Lattice Semiconductor Corporation
30-MAR-2012 2
iCE40 HX-Series Ultra-Low Power mobileFPGA Family

Electrical Characteristics

All parameter limits are specified under worst-case supply voltage, junction temperature, and processing conditions.

Absolute Maximum Ratings

Stresses beyond those listed under Table 2 may cause permanent damage to the device. These are stress ratings only functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied. Exposure to absolute maximum conditions for extended periods of time adversely affects device reliability.

VCC VPP_2V5 VPP_FAST VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 SPI_VCC

VIN_0 VIN_1 VIN_2 VIN_SPI VIN_3 VCCPLL

IOUT TJ TSTG

Table 2 Absolute Maximum Ratings

Minimum

Core supply Voltage

VPP_2V5 NVCM programming and operating supply

Optional fast NVCM programming supply

I/O bank supply voltage I/O Banks 0, 1, 2 and 3 plus SPI
interface

Maximum

Voltage applied to PIO pin within a specific I/O bank I/O Banks 0, 1, 2 and 3 plus SPI interface

Analog voltage supply to the Phase Locked Loop PLL DC output current per pin Junction temperature Storage temperature, no bias

Units

V mA °C °C

Recommended Operating Conditions

Table 3 Recommended Operating Conditions

VCC VPP_2V51

VPP_FAST2 SPI_VCC VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 SPI_VCC VCCPLL3 TA TPROG

Core supply voltage

High Performance, low-power

VPP_2V5 NVCM

Release from Power-on Reset
programming and operating Configure from NVCM
supply

NVCM programming

Optional fast NVCM programming supply

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICE40HX640-VQ100 Datasheet file may be downloaded here without warranties.

Datasheet ID: ICE40HX640-VQ100 645473