MC100ES6139DT

MC100ES6139DT Datasheet

Order number MC100ES6139 Rev 1, 06/2004

Part	Datasheet
MC100ES6139DT	MC100ES6139DT (pdf)

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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip The MC100ES6139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a µF capacitor. The common enable EN is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state therefore, for systems which utilize multiple ES6139s, the master reset MR input must be asserted to ensure synchronization. For systems which only use one ES6139, the MR pin need not be exercised as the internal divider design ensures synchronization between the ÷2/4 and the ÷4/5/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100ES Series contains temperature compensation. • Maximum Frequency GHz Typical • 50 ps Output-to-Output Skew • PECL Mode Operating Range VCC = V to V with VEE = 0 V • ECL Mode Operating Range VCC = 0 V with VEE = V to V • Open Input Default State • Synchronous Enable/Disable • Master Reset for Synchronization of Multiple Chips • VBB Output • LVDS and HSTL Input Compatible MC100ES6139 SCALE 2 1 DT SUFFIX 20 LEAD TSSOP PACKAGE CASE 948E-02 DW SUFFIX 20 LEAD SOIC PACKAGE CASE 751D-06 ORDERING INFORMATION Device MC100ES6139DT MC100ES6139DTR2 MC100ES6139DW MC100ES6139DWR2 Package TSSOP-20 TSSOP-20 SO-20 SO-20 Motorola, Inc. 2004 For More Information On This Product, Go to: Freescale Semiconductor, Inc... DIVSELb0 DIVSELb1 DIVSELa MC100ES6139 Freescale Semiconductor, Inc. VCC Q0 Q1 Q2 Q3 VEE 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VCC EN CLK VBB MR VCC Warning All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 20-Lead Pinout Top View DIVSELa CLK Table Pin Description Pin CLK1, CLK1 EN1 MR1 VBB Q0, Q1, Q0, Q1 Q2, Q3, Q2, Q3 DIVSELa1 DIVSELb01 DIVSELb11 VCC VEE Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff ÷2/4 Outputs ECL Diff ÷4/5/6 Outputs ECL Freq. Select Input ÷2/4 ECL Freq. Select Input ÷4/5/6 ECL Freq. Select Input ÷4/5/6 ECL Positive Supply ECL Negative Supply Pins will default low when left open. ÷2/4 Q0 MR DIVSELb0 DIVSELb1 ÷4/5/6 Q2 Figure Logic Diagram Table Function Tables X = Don’t Care Z = Low-to-High Transition ZZ = High-to-Low Transition Function Divide Hold Q0:3 Reset Q0:3 DIVSELa DIVSELb0 DIVSELb1 Q0:1 Outputs Divide by 2 Divide by 4 Q2:3 Outputs Divide by 4 Divide by 6 Divide by 5 Divide by 5 MOTOROLA TIMING SOLUTIONS For More Information On This Product, Go to: Freescale Semiconductor, Inc. CLK Q ÷2 Q ÷4 Q ÷5 Q ÷6 Figure Timing Diagram

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Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA
3.3V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip

The MC100ES6139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a µF capacitor.

The common enable EN is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

Upon startup, the internal flip-flops will attain a random state therefore, for systems which utilize multiple ES6139s, the master reset MR input must be asserted to ensure synchronization. For systems which only use one ES6139, the MR pin need not be exercised as the internal divider design ensures synchronization between the ÷2/4 and the ÷4/5/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation.

The 100ES Series contains temperature compensation.
• Maximum Frequency GHz Typical
• 50 ps Output-to-Output Skew
• PECL Mode Operating Range VCC = V to V with VEE = 0 V
• ECL Mode Operating Range VCC = 0 V with VEE = V to V
• Open Input Default State
• Synchronous Enable/Disable
• Master Reset for Synchronization of Multiple Chips
• VBB Output
• LVDS and HSTL Input Compatible

MC100ES6139

SCALE 2 1

DT SUFFIX 20 LEAD TSSOP PACKAGE

CASE 948E-02

DW SUFFIX 20 LEAD SOIC PACKAGE

CASE 751D-06
ORDERING INFORMATION

Device MC100ES6139DT MC100ES6139DTR2 MC100ES6139DW MC100ES6139DWR2

Package TSSOP-20 TSSOP-20

SO-20 SO-20

Motorola, Inc. 2004

For More Information On This Product, Go to:

Freescale Semiconductor, Inc... DIVSELb0 DIVSELb1 DIVSELa

MC100ES6139

Freescale Semiconductor, Inc.

VCC Q0 Q1 Q2 Q3 VEE 20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10

VCC EN

CLK VBB MR VCC

Warning All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.

Figure 20-Lead Pinout Top View

DIVSELa CLK

Table Pin Description

Pin CLK1, CLK1 EN1 MR1 VBB Q0, Q1, Q0, Q1 Q2, Q3, Q2, Q3 DIVSELa1 DIVSELb01 DIVSELb11 VCC VEE

Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff ÷2/4 Outputs ECL Diff ÷4/5/6 Outputs ECL Freq. Select Input ÷2/4 ECL Freq. Select Input ÷4/5/6 ECL Freq. Select Input ÷4/5/6 ECL Positive Supply ECL Negative Supply

Pins will default low when left open.
÷2/4 Q0

MR DIVSELb0 DIVSELb1
÷4/5/6 Q2

Figure Logic Diagram

Table Function Tables

X = Don’t Care Z = Low-to-High Transition ZZ = High-to-Low Transition

Function

Divide Hold Q0:3 Reset Q0:3

DIVSELa

DIVSELb0

DIVSELb1

Q0:1 Outputs

Divide by 2 Divide by 4

Q2:3 Outputs

Divide by 4 Divide by 6 Divide by 5 Divide by 5

MOTOROLA

TIMING SOLUTIONS

For More Information On This Product, Go to:

Freescale Semiconductor, Inc.

CLK Q ÷2 Q ÷4 Q ÷5 Q ÷6

Figure Timing Diagram

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Datasheet ID: MC100ES6139DT 635462