MC100ES6014DT

MC100ES6014DT Datasheet

The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended if the VBB output is used . HSTL and LVDS inputs can be used when the ES6014 is operating under PECL conditions.

Part	Datasheet
MC100ES6014DT	MC100ES6014DT (pdf)

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Freescale Semiconductor Technical Data V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended if the VBB output is used . HSTL and LVDS inputs can be used when the ES6014 is operating under PECL conditions. The ES6014 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open unterminated without affecting skew. The common enable EN is synchronous, outputs are enabled/disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock therefore, all associated specification limits are referenced to the negative edge of the clock input. The MC100ES6014, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the ES6014 to be used for high performance clock distribution in V or V systems. Single ended CLK input pin operation is limited to a VCC V in PECL mode, or VEE V in ECL mode. Designers can take advantage of the ES6014's performance to distribute low skew clocks across the backplane or the board. • 25 ps Within Device Skew • 400 ps Typical Propagation Delay • Maximum Frequency > 2 GHz Typical • The 100 Series Contains Temperature Compensation • PECL and HSTL Mode VCC = V to V with VEE = 0 V • ECL Mode VCC = 0 V with VEE = V to V • LVDS and HSTL Input Compatible • Open Input Default State • 20-Lead Pb-Free Package Available MC100ES6014 DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-03 EJ SUFFIX 20-LEAD TSSOP PACKAGE Pb-FREE PACKAGE CASE 948E-03 ORDERING INFORMATION Device Package MC100ES6014DT TSSOP-20 MC100ES6014DTR2 TSSOP-20 MC100ES6014EJ TSSOP-20 Pb-Free MC100ES6014EJR2 TSSOP-20 Pb-Free Freescale Semiconductor, Inc., All rights reserved. EN VCC CLK1 VBB CLK0 CLK_SEL VEE Warning All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 20-Lead Pinout Top View and Logic Diagram Table Pin Description Function CLK0, CLK0* ECL/PECL/HSTL CLK Input CLK1, CLK1* ECL/PECL/HSTL CLK Input Q0:4, Q0:4 ECL/PECL Outputs CLK_SEL* ECL/PECL Active Clock Select Input ECL Sync Enable Reference Voltage Output Positive Supply Negative Supply * Pins will default LOW when left open. ** Pins will default to VCC/2 when left open. Table Function Table CLK0 CLK1 CLK_SEL * On next negative transition of CLK0 or CLK1 Table General specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Thermal Resistance Junction-to-Ambient 0 LFPM, 20 TSSOP 500 LFPM, 20 TSSOP Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Value

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Freescale Semiconductor Technical Data

V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver

The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended if the VBB output is used . HSTL and LVDS inputs can be used when the ES6014 is operating under PECL conditions.

The ES6014 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.

To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open unterminated without affecting skew.

The common enable EN is synchronous, outputs are enabled/disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock therefore, all associated specification limits are referenced to the negative edge of the clock input.

The MC100ES6014, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the ES6014 to be used for high performance clock distribution in V or V systems. Single ended CLK input pin operation is limited to a VCC V in PECL mode, or VEE V in ECL mode. Designers can take advantage of the ES6014's performance to distribute low skew clocks across the backplane or the board.
• 25 ps Within Device Skew
• 400 ps Typical Propagation Delay
• Maximum Frequency > 2 GHz Typical
• The 100 Series Contains Temperature Compensation
• PECL and HSTL Mode VCC = V to V with VEE = 0 V
• ECL Mode VCC = 0 V with VEE = V to V
• LVDS and HSTL Input Compatible
• Open Input Default State
• 20-Lead Pb-Free Package Available

MC100ES6014

DT SUFFIX 20-LEAD TSSOP PACKAGE

CASE 948E-03

EJ SUFFIX 20-LEAD TSSOP PACKAGE

Pb-FREE PACKAGE CASE 948E-03
ORDERING INFORMATION

Device

Package

MC100ES6014DT

TSSOP-20

MC100ES6014DTR2

TSSOP-20

MC100ES6014EJ

TSSOP-20 Pb-Free

MC100ES6014EJR2 TSSOP-20 Pb-Free

Freescale Semiconductor, Inc., All rights reserved.

EN VCC CLK1 VBB CLK0 CLK_SEL VEE

Warning All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.

Figure 20-Lead Pinout Top View and Logic Diagram

Table Pin Description

Function

CLK0*, CLK0** ECL/PECL/HSTL CLK Input

CLK1*, CLK1** ECL/PECL/HSTL CLK Input

Q0:4, Q0:4

ECL/PECL Outputs

CLK_SEL*

ECL/PECL Active Clock Select Input

ECL Sync Enable

Reference Voltage Output

Positive Supply

Negative Supply
* Pins will default LOW when left open. ** Pins will default to VCC/2 when left open.

Table Function Table

CLK0

CLK1 CLK_SEL
* On next negative transition of CLK0 or CLK1

Table General specifications

Characteristics

Internal Input Pulldown Resistor

Internal Input Pullup Resistor

ESD Protection

Human Body Model Machine Model Charged Device Model

Thermal Resistance Junction-to-Ambient
0 LFPM, 20 TSSOP 500 LFPM, 20 TSSOP

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

Value

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Datasheet ID: MC100ES6014DT 635456