ICS9LPRS525AFLF

ICS9LPRS525AFLF Datasheet

ICS9LPRS525

Part	Datasheet
ICS9LPRS525AFLF	ICS9LPRS525AFLF (pdf)

Related Parts	Information
ICS9LPRS525AFLFT	ICS9LPRS525AFLFT

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DATASHEET 56-pin CK505 for Intel Systems ICS9LPRS525 Recommended Application 56-pin CK505 compatible clock, w/fully integrated Vreg and series resistors on differential outputs Output Features • 2 - CPU differential low power push-pull pairs • 7 - SRC differential push-pull pairs • 1 - CPU/SRC selectable differential low power push-pull pair • 1 - SRC/DOT selectable differential low power push-pull pair • 1 - SRC/SE selectable differential push-pull pair/Single-ended outputs • 5 - PCI, 33MHz • 1 - USB, 48MHz • 1 - REF, 14.318MHz Key Specifications • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 250ps • +/- 100ppm frequency accuracy on all outputs • SRC outputs meet PCIe Gen2 when sourced from PLL3 Features/Benefits: • Supports spread spectrum modulation, 0 to down spread • Supports CPU clks up to 400MHz • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Table 1 CPU Frequency Select Table FSLC2 B0b7 FSLB1 B0b6 0 1 0 1 FSLA1 B0b5 0 1 0 1 0 1 0 1 CPU MHz SRC PCI REF USB DOT MHz Reserved FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Pin Configuration PCI0/CR#_A 1 56 SCLK VDDPCI 2 PCI1/CR#_B 3 PCI2/TME 4 PCI3/CFG0 5 PCI4/SRC5_EN 6 PCI_F5/ITP_EN 7 GNDPCI 8 VDD48 9 USB_48MHz/FSLA 10 GND48 11 VDD96IO 12 DOTT_96_LRS/SRCT0_LRS 13 DOTC_96_LRS/SRCC0_LRS 14 GND 15 VDD 16 SRCT1_LRS/SE1 17 SRCC1_LRS/SE2 18 GND 19 VDDPLL3IO 20 SRCT2_LRS/SATAT_LRS 21 SRCC2_LRS/SATAC_LRS 22 GNDSRC 23 SRCT3_LRS/CR#_C 24 SRCC3_LRS/CR#_D 25 VDDSRCIO 26 SRCT4_LRS 27 SRCC4_LRS 28 9LPRS525 55 SDATA 54 REF0/FSLC/TEST_SEL 53 VDDREF 52 X1 51 X2 50 GNDREF 49 FSLB/TEST_MODE 48 CK_PWRGD/PD# 47 VDDCPU 46 CPUT0_LRS 45 CPUC0_LRS 44 GNDCPU 43 CPUT1_F_LRS 42 CPUC1_F_LRS 41 VDDCPUIO 40 NC 39 CPUT2_ITP_LRS/SRCT8_LRS 38 CPUC2_ITP_LRS/SRCC8_LRS 37 VDDSRCIO 36 SRCT7_LRS/CR#_F 35 SRCC7_LRS/CR#_E 34 GNDSRC 33 SRCT6_LRS 32 SRCC6_LRS 31 VDDSRC 30 PCI_STOP#/SRCT5_LRS 29 CPU_STOP#/SRCC5_LRS 56-SSOP & TSSOP IDTTM PC MAIN CLOCK ICS9LPRS525 PC MAIN CLOCK Pin Description PIN # PIN NAME 1 PCI0/CR#_A Ordering Information 9LPRS525AFLFT Example: XXXX A F LF T Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type IDTTM PC MAIN CLOCK ICS9LPRS525 PC MAIN CLOCK INDEX AREA SEATING PLANE aaa C 56-Lead mm. Body, mm. Pitch TSSOP 240 mil 20 mil In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS SEE VARIATIONS SEE VARIATIONS BASIC BASIC BASIC BASIC SEE VARIATIONS SEE VARIATIONS VARIATIONS D mm. Reference Doc. JEDEC Publicat ion 95, M O-153 10 -0 3 9 D inch Ordering Information 9LPRS525AGLFT Example: XXXX A G LF T Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type IDTTM PC MAIN CLOCK ICS9LPRS525 PC MAIN CLOCK Page # - 2,3,17 1 Byte 11, bit 5 is now reserved. 2 Byte 29, bits 7:6 default to 0.8X slew rate ‘10’ 3 Removed reference to STOP drive mode in Power management table. 4 Corrected REF slew rate control from Byte 29b3 to Byte 29b2. 5 Clarified description of Byte 11, bits 2 and 3 to reflect CK505 ME clock selection table. 10/10/2008 6 Marked as Reserved all bits that are not in the 56-pin version of the device Various 1 updated tables 2, 6 and 7 to clarify interaction of Config Modes with SRC1 10, 11, 19, A 4/28/2009 Released to final B 1/21/2010 Updated Power Groups table C 4/20/2010 Updated Abs Max table with Case Temp. parameter Innovate with IDT and accelerate your future networks. Contact: For Sales 800-345-7015 408-284-8200 Fax 408-284-2775 For Tech Support 408-284-6578 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 outside U.S. Asia Pacific and Japan IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone 65-6-744-3356 Fax 65-6-744-1764 Europe IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone 44-1372-363339 Fax 44-1372-378851 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

PDF Datasheet Preview

DATASHEET
56-pin CK505 for Intel Systems

ICS9LPRS525

Recommended Application 56-pin CK505 compatible clock, w/fully integrated Vreg and series resistors on differential outputs

Output Features
• 2 - CPU differential low power push-pull pairs
• 7 - SRC differential push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull pair
• 1 - SRC/DOT selectable differential low power push-pull pair
• 1 - SRC/SE selectable differential push-pull pair/Single-ended
outputs
• 5 - PCI, 33MHz
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz

Key Specifications
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on all outputs
• SRC outputs meet PCIe Gen2 when sourced from PLL3

Features/Benefits:
• Supports spread spectrum modulation, 0 to down spread
• Supports CPU clks up to 400MHz
• Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning

Table 1 CPU Frequency Select Table

FSLC2 B0b7

FSLB1 B0b6
0 1 0 1

FSLA1 B0b5
0 1 0 1 0 1 0 1

CPU MHz

SRC PCI REF USB DOT MHz

Reserved

FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.

Pin Configuration

PCI0/CR#_A 1
56 SCLK

VDDPCI 2 PCI1/CR#_B 3

PCI2/TME 4 PCI3/CFG0 5 PCI4/SRC5_EN 6 PCI_F5/ITP_EN 7

GNDPCI 8 VDD48 9

USB_48MHz/FSLA 10 GND48 11

VDD96IO 12 DOTT_96_LRS/SRCT0_LRS 13 DOTC_96_LRS/SRCC0_LRS 14

GND 15 VDD 16 SRCT1_LRS/SE1 17 SRCC1_LRS/SE2 18 GND 19 VDDPLL3IO 20 SRCT2_LRS/SATAT_LRS 21 SRCC2_LRS/SATAC_LRS 22 GNDSRC 23 SRCT3_LRS/CR#_C 24 SRCC3_LRS/CR#_D 25 VDDSRCIO 26 SRCT4_LRS 27 SRCC4_LRS 28
9LPRS525
55 SDATA 54 REF0/FSLC/TEST_SEL 53 VDDREF 52 X1 51 X2 50 GNDREF 49 FSLB/TEST_MODE 48 CK_PWRGD/PD# 47 VDDCPU 46 CPUT0_LRS 45 CPUC0_LRS 44 GNDCPU 43 CPUT1_F_LRS 42 CPUC1_F_LRS 41 VDDCPUIO 40 NC 39 CPUT2_ITP_LRS/SRCT8_LRS 38 CPUC2_ITP_LRS/SRCC8_LRS 37 VDDSRCIO 36 SRCT7_LRS/CR#_F 35 SRCC7_LRS/CR#_E 34 GNDSRC 33 SRCT6_LRS 32 SRCC6_LRS 31 VDDSRC 30 PCI_STOP#/SRCT5_LRS 29 CPU_STOP#/SRCC5_LRS
56-SSOP & TSSOP

IDTTM PC MAIN CLOCK

ICS9LPRS525 PC MAIN CLOCK

Pin Description

PIN #

PIN NAME
1 PCI0/CR#_A
Ordering Information
9LPRS525AFLFT

Example:

XXXX A F LF T

Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type

IDTTM PC MAIN CLOCK

ICS9LPRS525 PC MAIN CLOCK

INDEX AREA

SEATING PLANE
aaa C
56-Lead mm. Body, mm. Pitch TSSOP
240 mil
20 mil

In Millimeters

In Inches

SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS

SEE VARIATIONS

SEE VARIATIONS

BASIC

BASIC

BASIC

BASIC

SEE VARIATIONS

SEE VARIATIONS

VARIATIONS

D mm.

Reference Doc. JEDEC Publicat ion 95, M O-153
10 -0 3 9

D inch
Ordering Information
9LPRS525AGLFT

Example:

XXXX A G LF T

Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type

IDTTM PC MAIN CLOCK

ICS9LPRS525 PC MAIN CLOCK

Page # -
2,3,17
1 Byte 11, bit 5 is now reserved.
2 Byte 29, bits 7:6 default to 0.8X slew rate ‘10’
3 Removed reference to STOP drive mode in Power management table.
4 Corrected REF slew rate control from Byte 29b3 to Byte 29b2.
5 Clarified description of Byte 11, bits 2 and 3 to reflect CK505 ME clock selection table.
10/10/2008 6 Marked as Reserved all bits that are not in the 56-pin version of the device

Various
1 updated tables 2, 6 and 7 to clarify interaction of Config Modes with SRC1
10, 11, 19,
A 4/28/2009 Released to final

B 1/21/2010 Updated Power Groups table

C 4/20/2010 Updated Abs Max table with Case Temp. parameter

Innovate with IDT and accelerate your future networks. Contact:

For Sales
800-345-7015 408-284-8200 Fax 408-284-2775

For Tech Support
408-284-6578

Corporate Headquarters

Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 outside U.S.

Asia Pacific and Japan

IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone 65-6-744-3356 Fax 65-6-744-1764

Europe

IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone 44-1372-363339 Fax 44-1372-378851
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICS9LPRS525AFLF Datasheet file may be downloaded here without warranties.

Datasheet ID: ICS9LPRS525AFLF 636905