ZL30252LDG1

ZL30252LDG1 Datasheet

ZL30252, ZL30253

Part	Datasheet
ZL30252LDG1	ZL30252LDG1 (pdf)

PDF Datasheet Preview
Register Map Section • Input Clocks • Three inputs two differential/CMOS, one CMOS • Any input frequency from 1kHz to 1250MHz 1kHz to 300MHz for CMOS • Inputs continually monitored for activity and frequency accuracy • Automatic or manual reference switching • Low-Bandwidth DPLL • Programmable bandwidth, 14Hz to 500Hz • Attenuates jitter up to several UI • Freerun or digital hold on loss of all inputs • Digitally controlled phase adjustment • Low-Jitter Fractional-N APLL and 3 Outputs • Any output frequency from <1Hz to 1035MHz • High-resolution fractional frequency conversion with 0ppm error • Easy-to-configure, encapsulated design requires no external VCXO or loop filter components • Each output has independent dividers • Output jitter is typically to 0.28ps RMS 12kHz-20MHz integration band • Outputs are CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL • In 2xCMOS mode, the P and N pins can be different frequencies e.g. 125MHz and 25MHz ZL30252, ZL30253 3-Input, 3-Output Any-to-Any Clock Multiplier and Jitter Attenuator ICs Data Sheet March 2015 Ordering Information ZL30252LDG1 ZL30252LDF1 ZL30253LDG1 ZL30253LDF1 32 Pin QFN 32 Pin QFN 32 Pin QFN 32 Pin QFN Trays Tape and Reel Trays Tape and Reel Matte Tin Package size 5 x 5 mm -40C to +85C • Per-output supply pin with CMOS output voltages from 1.5V to 3.3V • Precise output alignment circuitry and peroutput phase adjustment • Per-output enable/disable and glitchless start/stop high or low • General Features • Automatic self-configuration at power-up from external ZL30252 or internal ZL30253 EEPROM up to four configs pin-selectable • Numerically controlled oscillator mode • Spread-spectrum modulation mode • Zero-delay mode with external feedback • SPI or I2C processor Interface • Easy-to-use evaluation software • Frequency conversion, jitter attenuation and frequency synthesis in a wide variety of equipment types IC1P, IC1N IC2P, IC2N IC3P/GPIO3 HSDIV1 HSDIV2 HSDIV3 Input Block Divider, Monitor, Selector Figure 10 xtal driver x2 DPLL Jitter Filtering, Digital Hold Figure 11 APLL HSDIV1 DIV1 to 4.2GHz, Fractional-N DIV2 Figure 12 HSDIV2 DIV3 Microprocessor Port SPI or I2C Serial and HW Control and Status Pins OC1P, OC1N VDDO1 OC2P, OC2N VDDO2 OC3P, OC3N VDDO3 RSTN AC0/GPIO0 AC1/GPIO1 TEST/GPIO2 IC3P/GPIO3 IF0/CSN IF1/MISO SCL/SCLK SDA/MOSI Figure 1 - Functional Block Diagram 1 Microsemi Confidential Copyright Microsemi Corporation. All Rights Reserved.

PDF Datasheet Preview

Register Map Section
• Input Clocks
• Three inputs two differential/CMOS, one CMOS
• Any input frequency from 1kHz to 1250MHz 1kHz to 300MHz for CMOS
• Inputs continually monitored for activity and frequency accuracy
• Automatic or manual reference switching
• Low-Bandwidth DPLL
• Programmable bandwidth, 14Hz to 500Hz
• Attenuates jitter up to several UI
• Freerun or digital hold on loss of all inputs
• Digitally controlled phase adjustment
• Low-Jitter Fractional-N APLL and 3 Outputs
• Any output frequency from <1Hz to 1035MHz
• High-resolution fractional frequency conversion with 0ppm error
• Easy-to-configure, encapsulated design requires no external VCXO or loop filter components
• Each output has independent dividers
• Output jitter is typically to 0.28ps RMS 12kHz-20MHz integration band
• Outputs are CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL
• In 2xCMOS mode, the P and N pins can be different frequencies e.g. 125MHz and 25MHz

ZL30252, ZL30253
3-Input, 3-Output Any-to-Any Clock Multiplier and Jitter Attenuator ICs

Data Sheet

March 2015
Ordering Information

ZL30252LDG1 ZL30252LDF1 ZL30253LDG1 ZL30253LDF1
32 Pin QFN 32 Pin QFN 32 Pin QFN 32 Pin QFN

Trays Tape and Reel Trays Tape and Reel

Matte Tin Package size 5 x 5 mm
-40C to +85C
• Per-output supply pin with CMOS output voltages from 1.5V to 3.3V
• Precise output alignment circuitry and peroutput phase adjustment
• Per-output enable/disable and glitchless start/stop high or low
• General Features
• Automatic self-configuration at power-up from external ZL30252 or internal ZL30253 EEPROM up to four configs pin-selectable
• Numerically controlled oscillator mode
• Spread-spectrum modulation mode
• Zero-delay mode with external feedback
• SPI or I2C processor Interface
• Easy-to-use evaluation software
• Frequency conversion, jitter attenuation and frequency synthesis in a wide variety of equipment types

IC1P, IC1N IC2P, IC2N IC3P/GPIO3

HSDIV1 HSDIV2 HSDIV3

Input Block

Divider, Monitor, Selector

Figure 10
xtal
driver x2

DPLL

Jitter Filtering, Digital Hold

Figure 11

APLL

HSDIV1

DIV1
to 4.2GHz, Fractional-N

DIV2

Figure 12

HSDIV2

DIV3

Microprocessor Port

SPI or I2C Serial and HW Control and Status Pins

OC1P, OC1N VDDO1 OC2P, OC2N VDDO2 OC3P, OC3N VDDO3

RSTN AC0/GPIO0 AC1/GPIO1 TEST/GPIO2 IC3P/GPIO3

IF0/CSN IF1/MISO SCL/SCLK SDA/MOSI

Figure 1 - Functional Block Diagram
1 Microsemi Confidential

Copyright Microsemi Corporation. All Rights Reserved.

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Datasheet ID: ZL30252LDG1 649218