ZL30236GGG2003D

ZL30236GGG2003D Datasheet

ZL30236 Dual Channel Universal

Part	Datasheet
ZL30236GGG2003D	ZL30236GGG2003D (pdf)

Related Parts	Information
ZL30236GGG20038	ZL30236GGG20038

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• Generates clock signals at power-up per user defined custom OTP One Time Programmable configuration • Dynamically configurable via SPI/I2C interface and volatile configuration registers • Two independently programmable clock generators output any clock rate from 1 kHz to 750 MHz • Precision clock generators output clocks with jitter below ps RMS for 10 G PHYs • Operates from a single crystal resonator, clock oscillator or voltage controlled oscillator • Supports programmable frequency offsets for clock margining or for use as a digitally controlled oscillator • Eight LVPECL outputs max rate 750 MHz • Four LVCMOS outputs max rate MHz ZL30236 Dual Channel Universal Clock Generator Data Sheet March 2015 Ordering Information ZL30236GGG2 100 Pin LBGA* 11mmx11mm Trays Pb Free Tin/Silver/Copper -40oC to +85oC • Timing for NPUs, FPGAs, Ethernet switches and PCIe switches • Timing for 10 Gigabit CDRs, Rapid-IO, PCIe, Serial MII, Star Fabric, Fibre Channel, XAUI • Processor clock, Processor bus clock, SDRAM clock, DDR clock Figure 1 - Functional Block Diagram Copyright 2015, Microsemi Corporation. All Rights Reserved. ZL30236 Data Sheet Table of Contents Pin Diagram 8 Pin Description. 9 Application Example 13 Functional Description 14 Frequency Synthesis Engine. 14 Dividers and Skew Management. 14 Output Multiplexer 15 Output Drivers 16 Master Clock Interface. 18 Clock Oscillator and Crystal Circuit 18 Power Up/Down Sequence 19 Power Supply Filtering. 19 Power on Reset and Initialization Circuit 20 Ultra Low Jitter Synthesizer Filter Components and Recommended Layout 21 Configuration and Control 22 Configuration Registers 22 Default Configuration 22 Custom OTP Configuration 22 SPI/I2C Configuration 22 Output Multiplexer Configuration and Programmability 22 Synthesizers Configuration and Programmability 22 Output Dividers and Skew Management Configuration and Programmability. 22 Output Drivers configuration and Programmability 22 GPIO Configuration and Programmability 23 Host Interface 25 Serial Peripheral Interface 25 Least Significant Bit LSB First Transmission Mode 26 Most Significant Bit MSB First Transmission Mode 26 SPI Burst Mode Operation 27 I2C Interface. 27 Register Map 29 Detailed Register Map 34 AC and DC Electrical Characteristics 69 Performance Characterization 77 Output Clocks RMS Jitter Generation 77 Output Clocks Cycle-to-Cycle Jitter Generation 77 Thermal Characteristics 78 Mechanical Drawing 79 Package Markings 80 100-pin BGA. Package Top Mark Format 80 Microsemi Corporation ZL30236 Data Sheet List of Tables Table 1 - Pin Description 9 Table 2 - Master Clock Frequency Selection 19 Table 3 - Serial Interface Selection 25 Table 4 - Register Map 31 Table 5 - Serial Peripheral Interface Timing. 74 Table 6 - I2C Serial Microport Timing 76 Table 7 - Jitter Generation Specifications - HPDIFF Outputs 77 Table 8 - Jitter Generation Specifications - HPOUT Outputs. 77 Table 9 - Jitter Generation Specifications - HPDIFF Outputs 77 Table 10 - Thermal Data 78 Table 11 - Package Marking Legend 80 Microsemi Corporation ZL30236 Data Sheet List of Figures Figure 1 - Functional Block Diagram 1 Figure 2 - Package Description 8 Figure 3 - Application Diagram. 13 Figure 4 - Output Clock Muxing Configuration 15 Figure 5 - Terminating LVPECL Outputs 16 Figure 6 - Terminating AC coupled LVPECL Outputs 17 Figure 7 - Terminating LVCMOS Outputs 17 Figure 8 - Clock Oscillator Circuit. 18 Figure 9 - Typical Power-Up Reset and Configuration Circuit 20 Figure 10 - APLL Filter Component Values 21 Figure 11 - Recommended Layout for Loop Filters 21 Figure 12 - Serial Interface Configuration 25 Figure 13 - Serial Peripheral Interface Functional Waveforms - LSB First Mode 26 Figure 14 - Serial Peripheral Interface Functional Waveforms - MSB First Mode 26 Figure 15 - Example of a Burst Mode Operation 27 Figure 16 - I2C Data Write Protocol 27 Figure 17 - I2C Data Read Protocol. 27 Figure 18 - I2C 7-bit Slave Address 28 Figure 19 - I2C Data Write Burst Mode 28 Figure 20 - I2C Data Read Burst Mode 28 Figure 21 - Accessing Multi-byte Register Values 29 Figure 22 - Timing Parameter Measurement Voltage Levels. 72 Figure 23 - Output Timing Referenced To hpclkout0/clkout0. 73 Figure 24 - Serial Peripheral Interface Timing - LSB First Mode 74 Figure 25 - Serial Peripheral Interface Timing - MSB First Mode 75 Figure 26 - I2C Serial Microport Timing 76 Figure 27 - Non-customized Device Top Mark. 80 Figure 28 - Custom Factory Programmed Device Top Mark 80 Microsemi Corporation ZL30236 Data Sheet Change Summary Below are the changes from the June 2012 issue to the March 2015 issue Page Item 1 Ordering information 22 Custom OTP Configuration 80 “Package Markings“ Change Removed ZL30236GGG Leaded version from the ordering information Removed reference to ZLAN-301 Added section 13 for package markings Below are the changes from the January 2012 issue to the June 2012 issue Page Item 73 Output to Output Alignment 33 Register 0xC6 - Chip_Revision_2 and 59 Change Added min/max values for tOUT2OUTD Updated chip_revision_2 register 0xC6 = 0x03 Below are the changes from the December 2011 issue to the January 2012 issue. Page 29 30 30 34 31 33, 59 Item Procedure for writing registers Time between two write accesses to the same register Reading from Sticky read Registers Register 0x00 - id_reg Register 0x0D - Sticky_r_lock Register 0xC6 Below are the changes from the July 2011 issue to the December 2011 issue. Page 30 34 31, 35 67 Item Reading from Sticky read Registers Register 0x00 - id_reg Register 0x0D Register 0xF7 Change Updated Sticky read procedure updated ready indication bit description Added register 0x0D Updated spurs_suppression register description Below are the changes from the June 2011 issue to the July 2011 issue. Microsemi Corporation ZL30236 Data Sheet 1, 9, 14, 16, 73 9, 10, 19, 20, 25, 34 8,9 14 22 46 48 51 53 69 69 77 Item Feature All items related the maximum rate of differential output clocks All items related waiting time after pwr_b pin goes high during reset procedure Pin diagram Figure-2 and Pin description Table-1 Section Section Table-4 Section Detailed Register Map Register synth0_post_div_C Register synth0_post_div_D Register synth1_post_div_C Register synth1_post_div_D DC Electrical Characteristics -Power Core DC Electrical Characteristics - High Performance Outputs DC Electrical Characteristics Output Clocks Jitter Generation Change OTP feature is added The maximum rate is updated from 720 MHz to 750MHz Waiting time after pwr_b pin goes high is changed from 30 ms to 50 ms Names for pin J1, J2, J9, J10,K1, K2, K9, and K10 are changed from ’IC’ to ’NC’ Updated for OTP feature • Section and are updated for three configuration methods:Default configuration, OTP configuration, and SPI/I2C configuration • Original section and are changed to section and For page_register at address 0x7F, there is no waiting time required between two write accesses. • Table description is updated for OTP feature • Register 0x01, 0x0E and 0x0F are added • Heading of first column is changed from “Page_Addr” to “Reg_Addr" Detailed description for new register 0x01, 0x0E, and 0x0F are added "Page_Address" is changed to "Register_Address" for registers which addresses are from 0x80 to 0x91 Bit[15:0] note added for odd post divider Bit[15:0] note added for odd post divider Bit[15:0] note added for odd post divider Bit[15:0] note added for odd post divider • "Power for Each Synthesis Engine” is changed to “Current for Each Synthesis Engine” • “PSYN” is changed to “ISYN” Note added for differential output voltage when differential frequency is higher than 720MHz All "AVDD-IO" symbols are replaced with "AVDD" Jitter measurement filter for 77.76MHz is changed from "12kHz-5MHz" to "12kHz-20MHz" Microsemi Corporation Page Item 78 Section ZL30236 Change Note added for Tjmax Data Sheet Below are the changes from the January 2011 issue to the June 2011 issue. Page Item 1 Ordering Information 77 Section 77 Section 77 Section Change Corrected package description in ordering information to LBGA. The section was renamed to "Output Clocks RMS Jitter Generation" Table 9 was created for cycle-to-cycle jitter generation Replaced drawing to reflect correct package description. Below are the changes from the November 2010 issue to the January 2011 issue. Page 6 10 23 25 62 66 Item Figure 2 Table 1 Serial Peripheral Interface Figure 15 Table - Recommended Operating Conditions Table - AC Electrical Characteristics - Outputs Table - AC Electrical Characteristics* - Outputs Table - AC Electrical Characteristics* - Outputs Change Names of pin B5, B6, H5, and H6 are changed from AVcore to Vcore Names of pin B5, B6, H5, and H6 are changed from AVcore to Vcore, and they are merged to the same entry with pin D5, G5, and G6. Layout application note is referred SPI burst mode operation description is added Example of a Burst Mode Operation is added Row 2, AVcore is removed from the "Sym" column Correct wrong row numbers Row 2, clock duty cycle is changed from "43%-57%" to "45%-55%" Row 3, note "From 0.2AVDD-IO to 0.8AVDD-IO" is removed Microsemi Corporation Pin Diagram ZL30236 Data Sheet A hpdiff3_p avss filter1 avss hpdiff3_n avss filter1_ref avdd C hpdiff2_p hpdiff2_n avss gpio5 osco osci avss filter2 avss hpdiff7_p vcore vcore pwr_b filter2_ref avss hpdiff7_n gpio0 avss

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• Generates clock signals at power-up per user defined custom OTP One Time Programmable configuration
• Dynamically configurable via SPI/I2C interface and volatile configuration registers
• Two independently programmable clock generators output any clock rate from 1 kHz to 750 MHz
• Precision clock generators output clocks with jitter below ps RMS for 10 G PHYs
• Operates from a single crystal resonator, clock oscillator or voltage controlled oscillator
• Supports programmable frequency offsets for clock margining or for use as a digitally controlled oscillator
• Eight LVPECL outputs max rate 750 MHz
• Four LVCMOS outputs max rate MHz

ZL30236 Dual Channel Universal

Clock Generator

Data Sheet

March 2015
Ordering Information ZL30236GGG2 100 Pin LBGA* 11mmx11mm Trays
*Pb Free Tin/Silver/Copper -40oC to +85oC
• Timing for NPUs, FPGAs, Ethernet switches and PCIe switches
• Timing for 10 Gigabit CDRs, Rapid-IO, PCIe, Serial MII, Star Fabric, Fibre Channel, XAUI
• Processor clock, Processor bus clock, SDRAM clock, DDR clock

Figure 1 - Functional Block Diagram

Copyright 2015, Microsemi Corporation. All Rights Reserved.

ZL30236

Data Sheet

Table of Contents

Pin Diagram 8

Pin Description. 9

Application Example 13

Functional Description 14 Frequency Synthesis Engine. 14 Dividers and Skew Management. 14 Output Multiplexer 15 Output Drivers 16 Master Clock Interface. 18 Clock Oscillator and Crystal Circuit 18 Power Up/Down Sequence 19 Power Supply Filtering. 19 Power on Reset and Initialization Circuit 20 Ultra Low Jitter Synthesizer Filter Components and Recommended Layout 21

Configuration and Control 22 Configuration Registers 22 Default Configuration 22 Custom OTP Configuration 22 SPI/I2C Configuration 22 Output Multiplexer Configuration and Programmability 22 Synthesizers Configuration and Programmability 22 Output Dividers and Skew Management Configuration and Programmability. 22 Output Drivers configuration and Programmability 22 GPIO Configuration and Programmability 23

Host Interface 25 Serial Peripheral Interface 25 Least Significant Bit LSB First Transmission Mode 26 Most Significant Bit MSB First Transmission Mode 26 SPI Burst Mode Operation 27 I2C Interface. 27

Register Map 29

Detailed Register Map 34

AC and DC Electrical Characteristics 69

Performance Characterization 77 Output Clocks RMS Jitter Generation 77 Output Clocks Cycle-to-Cycle Jitter Generation 77

Thermal Characteristics 78

Mechanical Drawing 79

Package Markings 80 100-pin BGA. Package Top Mark Format 80

Microsemi Corporation

ZL30236

Data Sheet

List of Tables

Table 1 - Pin Description 9 Table 2 - Master Clock Frequency Selection 19 Table 3 - Serial Interface Selection 25 Table 4 - Register Map 31 Table 5 - Serial Peripheral Interface Timing. 74 Table 6 - I2C Serial Microport Timing 76 Table 7 - Jitter Generation Specifications - HPDIFF Outputs 77 Table 8 - Jitter Generation Specifications - HPOUT Outputs. 77 Table 9 - Jitter Generation Specifications - HPDIFF Outputs 77 Table 10 - Thermal Data 78 Table 11 - Package Marking Legend 80

Microsemi Corporation

ZL30236

Data Sheet

List of Figures

Figure 1 - Functional Block Diagram 1 Figure 2 - Package Description 8 Figure 3 - Application Diagram. 13 Figure 4 - Output Clock Muxing Configuration 15 Figure 5 - Terminating LVPECL Outputs 16 Figure 6 - Terminating AC coupled LVPECL Outputs 17 Figure 7 - Terminating LVCMOS Outputs 17 Figure 8 - Clock Oscillator Circuit. 18 Figure 9 - Typical Power-Up Reset and Configuration Circuit 20 Figure 10 - APLL Filter Component Values 21 Figure 11 - Recommended Layout for Loop Filters 21 Figure 12 - Serial Interface Configuration 25 Figure 13 - Serial Peripheral Interface Functional Waveforms - LSB First Mode 26 Figure 14 - Serial Peripheral Interface Functional Waveforms - MSB First Mode 26 Figure 15 - Example of a Burst Mode Operation 27 Figure 16 - I2C Data Write Protocol 27 Figure 17 - I2C Data Read Protocol. 27 Figure 18 - I2C 7-bit Slave Address 28 Figure 19 - I2C Data Write Burst Mode 28 Figure 20 - I2C Data Read Burst Mode 28 Figure 21 - Accessing Multi-byte Register Values 29 Figure 22 - Timing Parameter Measurement Voltage Levels. 72 Figure 23 - Output Timing Referenced To hpclkout0/clkout0. 73 Figure 24 - Serial Peripheral Interface Timing - LSB First Mode 74 Figure 25 - Serial Peripheral Interface Timing - MSB First Mode 75 Figure 26 - I2C Serial Microport Timing 76 Figure 27 - Non-customized Device Top Mark. 80 Figure 28 - Custom Factory Programmed Device Top Mark 80

Microsemi Corporation

ZL30236

Data Sheet

Change Summary

Below are the changes from the June 2012 issue to the March 2015 issue
Page Item 1 Ordering information
22 Custom OTP Configuration 80 “Package Markings“
Change Removed ZL30236GGG Leaded version from the ordering information Removed reference to ZLAN-301 Added section 13 for package markings

Below are the changes from the January 2012 issue to the June 2012 issue

Page Item
73 Output to Output Alignment
33 Register 0xC6 - Chip_Revision_2 and 59

Change Added min/max values for tOUT2OUTD Updated chip_revision_2 register 0xC6 = 0x03

Below are the changes from the December 2011 issue to the January 2012 issue.

Page 29 30
30 34 31 33, 59

Item

Procedure for writing registers Time between two write accesses to the same register Reading from Sticky read Registers Register 0x00 - id_reg Register 0x0D - Sticky_r_lock Register 0xC6

Below are the changes from the July 2011 issue to the December 2011 issue.

Page 30 34 31, 35 67

Item Reading from Sticky read Registers Register 0x00 - id_reg Register 0x0D

Register 0xF7

Change Updated Sticky read procedure updated ready indication bit description Added register 0x0D

Updated spurs_suppression register description

Below are the changes from the June 2011 issue to the July 2011 issue.

Microsemi Corporation

ZL30236

Data Sheet
1, 9, 14, 16, 73 9, 10, 19, 20, 25, 34 8,9
14 22
46 48 51 53 69
69 77

Item Feature All items related the maximum rate of differential output clocks

All items related waiting time after pwr_b pin goes high during reset procedure

Pin diagram Figure-2 and Pin description Table-1 Section

Section Table-4

Section Detailed Register Map Register synth0_post_div_C Register synth0_post_div_D Register synth1_post_div_C Register synth1_post_div_D DC Electrical Characteristics -Power Core DC Electrical Characteristics - High Performance Outputs DC Electrical Characteristics Output Clocks Jitter Generation

Change OTP feature is added The maximum rate is updated from 720 MHz to 750MHz

Waiting time after pwr_b pin goes high is changed from 30 ms to 50 ms

Names for pin J1, J2, J9, J10,K1, K2, K9, and K10 are changed from ’IC’ to ’NC’ Updated for OTP feature
• Section and are
updated for three configuration methods:Default configuration, OTP configuration, and SPI/I2C configuration
• Original section and are changed to section and For page_register at address 0x7F, there is no waiting time required between two write accesses.
• Table description is updated for OTP feature
• Register 0x01, 0x0E and 0x0F are added
• Heading of first column is changed from “Page_Addr” to “Reg_Addr" Detailed description for new register 0x01, 0x0E, and 0x0F are added "Page_Address" is changed to "Register_Address" for registers which addresses are from 0x80 to 0x91 Bit[15:0] note added for odd post divider Bit[15:0] note added for odd post divider Bit[15:0] note added for odd post divider Bit[15:0] note added for odd post divider
• "Power for Each Synthesis Engine” is changed to “Current for Each Synthesis Engine”
• “PSYN” is changed to “ISYN” Note added for differential output voltage when differential frequency is higher than 720MHz All "AVDD-IO" symbols are replaced with "AVDD" Jitter measurement filter for 77.76MHz is changed from "12kHz-5MHz" to "12kHz-20MHz"

Microsemi Corporation

Page Item 78 Section

ZL30236

Change Note added for Tjmax

Data Sheet

Below are the changes from the January 2011 issue to the June 2011 issue.
Page Item 1 Ordering Information
77 Section
77 Section 77 Section

Change
Corrected package description in ordering information to LBGA.

The section was renamed to "Output Clocks RMS Jitter Generation"

Table 9 was created for cycle-to-cycle jitter generation

Replaced drawing to reflect correct package description.

Below are the changes from the November 2010 issue to the January 2011 issue.

Page 6 10
23 25 62 66

Item Figure 2

Table 1

Serial Peripheral Interface Figure 15 Table - Recommended Operating Conditions Table - AC Electrical Characteristics* - Outputs Table - AC Electrical Characteristics* - Outputs Table - AC Electrical Characteristics* - Outputs

Change Names of pin B5, B6, H5, and H6 are changed from AVcore to Vcore Names of pin B5, B6, H5, and H6 are changed from AVcore to Vcore, and they are merged to the same entry with pin D5, G5, and G6. Layout application note is referred SPI burst mode operation description is added Example of a Burst Mode Operation is added Row 2, AVcore is removed from the "Sym" column

Correct wrong row numbers

Row 2, clock duty cycle is changed from "43%-57%" to "45%-55%" Row 3, note "From 0.2AVDD-IO to 0.8AVDD-IO" is removed

Microsemi Corporation

Pin Diagram

ZL30236

Data Sheet

A hpdiff3_p
avss
filter1
avss
hpdiff3_n
avss
filter1_ref
avdd

C hpdiff2_p hpdiff2_n
avss
gpio5
osco
osci
avss
filter2
avss
hpdiff7_p
vcore
vcore
pwr_b filter2_ref
avss
hpdiff7_n
gpio0
avss

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Datasheet ID: ZL30236GGG2003D 649215