MT90820AL1

MT90820AL1 Datasheet

CMOS ST-BUSTM Family MT90820 Large Digital Switch

Part	Datasheet
MT90820AL1	MT90820AL1 (pdf)

PDF Datasheet Preview
CMOS ST-BUSTM Family MT90820 Large Digital Switch Data Sheet • 2,048 x 2,048 channel non-blocking switching at Mb/s • Per-channel variable or constant throughput delay • Automatic identification of ST-BUS/GCI interfaces • Accept ST-BUS streams of Mb/s, Mb/s or Mb/s • Automatic frame offset delay measurement • Per-stream frame delay offset programming • Per-channel high impedance output control • Per-channel message mode • Control interface compatible to Motorola non- mulitplexed CPUs • Connection memory block programming • IEEE-1149.1 JTAG Test Port August 2005 Ordering Information MT90820AP 84 Pin PLCC MT90820AL 100 Pin MQFP MT90820APR 84 Pin PLCC MT90820AL1 100 Pin MQFP* MT90820AP1 84 Pin PLCC* MT90820APR1 84 Pin PLCC* *Pb Free Matte Tin -40°C to +85°C Tubes Trays Tape & Reel Trays Tubes Tape & Reel • Medium and large switching platforms • CTI application • Voice/data multiplexer • Digital cross connects • ST-BUS/GCI interface functions • Support IEEE 802.9a standard STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 VDD VSS Serial to Parallel Converter TMS TDI TDO TCK TRST IC RESET Test Port Loopback Multiple Buffer Data Memory Internal Registers Output MUX Connection Memory Parallel to Serial Converter Timing Unit Microprocessor Interface CLK F0i FE/ WFPS HCLK AS/ ALE DS/ RD R/W /WR A7-A0 DTA D15-D8/ CSTo AD7-AD0 Figure 1 - Functional Block Diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2000-2005, Zarlink Semiconductor Inc. All Rights Reserved. STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15 MT90820 Data Sheet The MT90820 Large Digital Switch has a non-blocking switch capacity of 2,048 x 2,048 channels at a serial bit rate of Mb/s, 1,024 x 1,024 channels at Mb/s and 512 x 512 channels at Mb/s. The device has many features that are programmable on per stream or per channel basis, including message mode, input offset delay and high impedance output control. Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice channel and concatenated data channels.

PDF Datasheet Preview

CMOS ST-BUSTM Family MT90820 Large Digital Switch

Data Sheet
• 2,048 x 2,048 channel non-blocking switching at Mb/s
• Per-channel variable or constant throughput delay
• Automatic identification of ST-BUS/GCI interfaces
• Accept ST-BUS streams of Mb/s,

Mb/s or Mb/s
• Automatic frame offset delay measurement
• Per-stream frame delay offset programming
• Per-channel high impedance output control
• Per-channel message mode
• Control interface compatible to Motorola non-
mulitplexed CPUs
• Connection memory block programming
• IEEE-1149.1 JTAG Test Port

August 2005
Ordering Information

MT90820AP 84 Pin PLCC

MT90820AL
100 Pin MQFP

MT90820APR 84 Pin PLCC

MT90820AL1 100 Pin MQFP*

MT90820AP1 84 Pin PLCC*

MT90820APR1 84 Pin PLCC*
*Pb Free Matte Tin
-40°C to +85°C

Tubes Trays Tape & Reel Trays Tubes

Tape & Reel
• Medium and large switching platforms
• CTI application
• Voice/data multiplexer
• Digital cross connects
• ST-BUS/GCI interface functions
• Support IEEE 802.9a standard

STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15

VDD VSS

Serial to

Parallel Converter

TMS TDI TDO TCK TRST IC RESET

Test Port

Loopback

Multiple Buffer Data Memory

Internal Registers

Output MUX

Connection Memory

Parallel to

Serial Converter

Timing Unit

Microprocessor Interface

CLK F0i FE/ WFPS HCLK

AS/ ALE

DS/ RD

R/W /WR

A7-A0 DTA D15-D8/ CSTo AD7-AD0

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 2000-2005, Zarlink Semiconductor Inc. All Rights Reserved.

STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15

MT90820

Data Sheet

The MT90820 Large Digital Switch has a non-blocking switch capacity of 2,048 x 2,048 channels at a serial bit rate of Mb/s, 1,024 x 1,024 channels at Mb/s and 512 x 512 channels at Mb/s. The device has many features that are programmable on per stream or per channel basis, including message mode, input offset delay and high impedance output control.

Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice channel and concatenated data channels.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT90820AL1 Datasheet file may be downloaded here without warranties.

Datasheet ID: MT90820AL1 649085