MT4VDDT864HG-26AB2

MT4VDDT864HG-26AB2 Datasheet

MT4VDDT864H 64MB MT4VDDT1664H 128MB MT4VDDT3264H 256MB

Part	Datasheet
MT4VDDT864HG-26AB2	MT4VDDT864HG-26AB2 (pdf)

Related Parts	Information
MT4VDDT3264HG-335F2	MT4VDDT3264HG-335F2
MT4VDDT1664HG-265F3	MT4VDDT1664HG-265F3
MT4VDDT1664HG-335F3	MT4VDDT1664HG-335F3

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64MB, 128MB, 256MB x64, SR 200-PIN DDR SDRAM SODIMM DDR SDRAM SMALLOUTLINE DIMM MT4VDDT864H 64MB MT4VDDT1664H 128MB MT4VDDT3264H 256MB For the latest data sheet, please refer to the Web site: • 200-pin, small-outline, dual in-line memory module DDR SODIMM • Fast data transfer rates PC2100 or PC2700 • Utilizes 266 MT/s and 333 MT/s DDR SDRAM components • 64MB 8 Meg x 64 , 128MB 16 Meg x 64 , and 256MB 32 Meg x 64 • VDD= VDDQ= +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/ received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Selectable burst lengths 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh Modes 15.625µs 64MB 7.8125µs 128MB, 256MB maximum average periodic refresh interval • Serial Presence Detect SPD with EEPROM • Selectable READ CAS latency for maximum compatibility • Gold edge contacts Figure 1 200-Pin SODIMM MO-224 1.25in. 31.75mm OPTIONS • Package 200-pin SODIMM standard 200-pin SODIMM lead-free 1 • Memory Clock, Speed, CAS Latency2 6ns 167 MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = • PCB 1.25in. 31.75mm MARKING -335 -2621 -26A1 -265 NOTE Consult factory for product availability. CL = Device CAS READ Latency. Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 64MB 4K 4 BA0, BA1 128Mb 8 Meg x 16 512 1 S0# 128MB 8K 4 BA0, BA1 256Mb 16 Meg x 16 512 1 S0# 256MB 8K 4 BA0, BA1 512Mb 32 Meg x 16 1K 1 S0# 2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 64MB, 128MB, 256MB x64, SR 200-PIN DDR SDRAM SODIMM Table 2 Part Numbers and Timing Parameters MODULE MODULE MEMORY CLOCK/ CLOCK LATENCY DENSITY CONFIGURATION BANDWIDTH DATA RATE CL - tRCD - tRP The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Figure 6, Burst Definition Table, on page Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 6, CAS Latency Diagram, on page If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 10, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. 64MB, 128MB, 256MB x64, SR 200-PIN DDR SDRAM SODIMM Figure 5 Mode Register Definition Diagram 64MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M13 and M12 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . 128MB and 256MB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 Reserved 2 4 8 Reserved M3 = 1 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 Reserved M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. Table 6 Burst Definition Table STARTING BURST COLUMN LENGTH ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED A1 A0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2

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64MB, 128MB, 256MB x64, SR 200-PIN DDR SDRAM SODIMM

DDR SDRAM SMALLOUTLINE DIMM

MT4VDDT864H 64MB MT4VDDT1664H 128MB MT4VDDT3264H 256MB

For the latest data sheet, please refer to the Web
site:
• 200-pin, small-outline, dual in-line memory module DDR SODIMM
• Fast data transfer rates PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• 64MB 8 Meg x 64 , 128MB 16 Meg x 64 , and
256MB 32 Meg x 64
• VDD= VDDQ= +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/
received with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Selectable burst lengths 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes 15.625µs 64MB 7.8125µs 128MB, 256MB maximum average periodic refresh interval
• Serial Presence Detect SPD with EEPROM
• Selectable READ CAS latency for maximum compatibility
• Gold edge contacts

Figure 1 200-Pin SODIMM MO-224
1.25in. 31.75mm

OPTIONS
• Package 200-pin SODIMM standard 200-pin SODIMM lead-free 1
• Memory Clock, Speed, CAS Latency2 6ns 167 MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL =
• PCB 1.25in. 31.75mm

MARKING
-335 -2621 -26A1 -265

NOTE Consult factory for product availability. CL = Device CAS READ Latency.

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
64MB
4K 4 BA0, BA1 128Mb 8 Meg x 16 512
1 S0#
128MB
8K 4 BA0, BA1 256Mb 16 Meg x 16 512
1 S0#
256MB
8K 4 BA0, BA1 512Mb 32 Meg x 16 1K
1 S0#
2004 Micron Technology, Inc. All rights reserved.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
64MB, 128MB, 256MB x64, SR 200-PIN DDR SDRAM SODIMM

Table 2 Part Numbers and Timing Parameters

MODULE

MODULE MEMORY CLOCK/ CLOCK LATENCY

DENSITY CONFIGURATION BANDWIDTH

DATA RATE

CL - tRCD - tRP
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Figure 6, Burst Definition Table, on page

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 6, CAS Latency Diagram, on page

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 10, indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.
64MB, 128MB, 256MB x64, SR 200-PIN DDR SDRAM SODIMM

Figure 5 Mode Register Definition Diagram
64MB Module

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .
128MB and 256MB Modules

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

Burst Length

M3 = 0 Reserved
2 4 8 Reserved

M3 = 1 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 Reserved

M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.

Table 6 Burst Definition Table

STARTING BURST COLUMN LENGTH ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

A1 A0
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2

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Datasheet ID: MT4VDDT864HG-26AB2 648475