MT90401AB1

MT90401AB1 Datasheet

MT90401 SONET/SDH System Synchronizer

Part	Datasheet
MT90401AB1	MT90401AB1 (pdf)

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MT90401 SONET/SDH System Synchronizer Data Sheet • Meets requirements of GR-253-CORE for SONET Stratum 3 and SONET minimum clock • Meets requirements of GR-1244-CORE Stratum 3 • Meets requirements of G.813 Option 1 and Option 2 for SDH Equipment Clocks SEC with external jitter attenuator • Provides OC-3/STM-1, DS3, E3, MHz, DS2, E1, T1, 8 kHz and ST-BUS clock outputs • Accepts reference inputs from two independent sources • Selectable MHz, MHz, MHz or 8kHz input reference frequencies • Holdover accuracy of ppm • Adjustable output clock phase supporting masterslave arrangements • Hardware or microprocessor control 8 bit microprocessor interface • V supply • JTAG boundary scan January 2005 Ordering Information MT90401AB 80 Pin LQFP MT90401AB1 80 Pin LQFP* *Pb Free Matte Tin -40°C to +85°C Trays • SONET/SDH Add/Drop multiplexers • SONET/SDH uplinks • Integrated access devices • ATM edge switches The MT90401 is a digital phase locked loop DPLL that is designed to synchronize SDH Synchronous Digital Hierarchy and SONET Synchronous Optical Network networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by Telcordia, ANSI and the ITU during normal operation and in the presence of disturbances on the incoming synchronization signals. C20i TCK TDI TMS TRST TDO PRI SEC Prioor Secoor RSEL TCLR LOCK VDD VSS Master Clock IEEE 1149.1a TIE Corrector Circuit Virtual Reference Reference Select MUX Reference Monitor Selected Reference TIE Corrector Enable Reference Select State Select Control State Machine DPLL State Select Input Impairment Monitor Feedback Output Interface Circuit Frequency Select MUX C155P/N C19o C1.5o C2o C6o C8o C16o C44/C34 F0o F16o RST MS1 MS2 HOLDOVERPCCi FLOCK D0/D7 A0/A6 CS,DS,R/W FS1 FS2 Figure 1 - Functional Block Diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. MT90401 Data Sheet The MT90401 can operate in free-run, locked or holdover mode. The loop filter corner frequency can be selected to suit SONET applications or to suit SDH applications. The MT90401 uses an external 20 MHz oscillator as its master clock and it does not require external loop filter components. In Hardware Mode, the MT90401 can be controlled and monitored via external pins. In Microport Mode, a microprocessor can be used for more comprehensive control and monitoring.

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MT90401 SONET/SDH System Synchronizer

Data Sheet
• Meets requirements of GR-253-CORE for SONET Stratum 3 and SONET minimum clock
• Meets requirements of GR-1244-CORE Stratum 3
• Meets requirements of G.813 Option 1 and Option 2 for SDH Equipment Clocks SEC with external jitter attenuator
• Provides OC-3/STM-1, DS3, E3, MHz, DS2, E1, T1, 8 kHz and ST-BUS clock outputs
• Accepts reference inputs from two independent sources
• Selectable MHz, MHz, MHz or 8kHz input reference frequencies
• Holdover accuracy of ppm
• Adjustable output clock phase supporting masterslave arrangements
• Hardware or microprocessor control 8 bit microprocessor interface
• V supply
• JTAG boundary scan

January 2005
Ordering Information

MT90401AB 80 Pin LQFP MT90401AB1 80 Pin LQFP*
*Pb Free Matte Tin
-40°C to +85°C

Trays
• SONET/SDH Add/Drop multiplexers
• SONET/SDH uplinks
• Integrated access devices
• ATM edge switches

The MT90401 is a digital phase locked loop DPLL that is designed to synchronize SDH Synchronous Digital Hierarchy and SONET Synchronous Optical Network networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by Telcordia, ANSI and the ITU during normal operation and in the presence of disturbances on the incoming synchronization signals.

C20i TCK TDI TMS TRST TDO PRI SEC

Prioor Secoor

RSEL

TCLR

LOCK VDD VSS

Master Clock

IEEE 1149.1a

TIE Corrector

Circuit

Virtual Reference

Reference Select MUX

Reference Monitor

Selected Reference

TIE Corrector

Enable

Reference Select

State Select

Control State Machine

DPLL

State Select Input Impairment Monitor

Feedback

Output Interface Circuit

Frequency Select MUX

C155P/N C19o C1.5o C2o

C6o C8o C16o C44/C34 F0o

F16o

RST MS1 MS2 HOLDOVERPCCi FLOCK D0/D7 A0/A6 CS,DS,R/W FS1 FS2

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.

MT90401

Data Sheet

The MT90401 can operate in free-run, locked or holdover mode. The loop filter corner frequency can be selected to suit SONET applications or to suit SDH applications. The MT90401 uses an external 20 MHz oscillator as its master clock and it does not require external loop filter components.

In Hardware Mode, the MT90401 can be controlled and monitored via external pins. In Microport Mode, a microprocessor can be used for more comprehensive control and monitoring.

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Datasheet ID: MT90401AB1 649083