LE58QL021BVC

LE58QL021BVC Datasheet

Le58QL02/021/031

Part	Datasheet
LE58QL021BVC	LE58QL021BVC (pdf)

Related Parts	Information
LE58QL021BVCT	LE58QL021BVCT
LE58QL021FJCT	LE58QL021FJCT
LE58QL031DJCT	LE58QL031DJCT
LE58QL02FJCT	LE58QL02FJCT
LE58QL02FJC	LE58QL02FJC
LE58QL031DJC	LE58QL031DJC
LE58QL021FJC	LE58QL021FJC

PDF Datasheet Preview
Le58QL02/021/031 Quad Low Voltage Subscriber Line Audio-Processing Circuit VE580 Series - Codec function on telephone switch line cards - Low-power, V CMOS technology with 5-V tolerant digital inputs - Software and coefficient compatible to the Le79Q02/ 021/031 QSLAC device - Performs the functions of four codec/filters - Software programmable: SLIC device input impedance Transhybrid balance Transmit and receive gains Equalization frequency response Digital I/O pins Programmable debouncing on one input Time slot assigner Programmable clock slot and PCM transmit clock edge options - Standard microprocessor interface - A-law, µ-law, or linear coding - Single or Dual PCM ports available Up to 128 channels PCLK at MHz per PCM port Optional supervision on the PCM highway - or MHz master clock derived from MCLK or PCLK - Built-in test modes with loopback, tone generation, and µP access to PCM data - Mixed state analog and digital impedance scaling - Performance guaranteed over a 12 dB gain range - Real Time Data register with interrupt open drain or TTL output - Supports multiplexed SLIC device outputs - Broadcast state - 256 kHz or 293 kHz chopper clock for Legerity SLIC devices with switching regulator - Maximum channel bandwidth for V.90 modems RELATED LITERATURE - 080754 Le58QL061/063 QLSLAC Device Data Sheet - 080761 QSLAC to QLSLAC Device Design Conversion Guide - 080758 QSLAC to QLSLAC Guide to New Designs ORDERING INFORMATION Device Package Green 1 Packing2 Le58QL02FJC 44-pin PLCC Tube Le58QL021FJC 44-pin PLCC Tube Le58QL021BVC 44-pin TQFP Tray Le58QL031DJC 32-pin PLCC Tube The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. For delivery using a tape and reel packing system, add a "T" suffix to the OPN Ordering Part Number when placing an order. The Le58QL02/021/031 Quad Low Voltage Subscriber Line Audio-Processing Circuit QLSLAC devices integrate the key functions of analog line cards into high-performance, veryprogrammable, four-channel codec-filter devices. The QLSLAC devices are based on the proven design of Legerity’s reliable SLAC device families. The advanced architecture of the QLSLAC devices implements four independent channels and employs digital filters to allow software control of transmission, thus providing a cost-effective solution for the audio-processing function of programmable line cards. The QLSLAC devices are software and coefficient compatible to the QSLAC devices. Advanced submicron CMOS technology makes the Le58QL02/ 021/031 QLSLAC devices economical, with both the functionality and the low power consumption needed in line card designs to maximize line card density at minimum cost. When used with four Legerity SLIC devices, a QLSLAC device provides a complete software-configurable solution to the BORSCHT functions. BLOCK DIAGRAM Analog VIN1 VOUT 1 VIN2 VOUT 2 VIN3 VOUT 3 VIN4 VOUT 4 VREF SLIC CD11 CD21 C31 C41 C51 CD12 CD22 C32 C42 C52 CD13 CD23 C33 C43 C53 CD14 CD24 C34 C44 C54 CHCLK Signal Processing Channel 1 CH 1 Signal Processing Channel 2 CH 2 Signal Processing Channel 3 CH 3 Signal Processing Channel 4 CH 4 Clock & Reference Circuits Time Slot Assigner TSA SLIC Interface Microprocessor Interface MPI INT CS DIO DCLK Microprocessor Dual/Single PCM Highway DXA DRA TSCA DXB DRB TSCB FS PCLK MCLK/E1 Document ID# 080753 Date April 09, 2009 Version: Distribution Public Document Le58QL02/021/031 Data Sheet TABLE OF CONTENTS ORDERING INFORMATION. RELATED LITERATURE BLOCK DIAGRAM TABLE OF CONTENTS LIST OF FIGURES LIST OF TABLES PRODUCT DESCRIPTION BLOCK DESCRIPTIONS Clock and Reference Circuits Microprocessor Interface MPI Time Slot Assigner TSA Signal Processing Channels CHx SLIC Device Interface SLI CONNECTION DIAGRAMS PIN DESCRIPTIONS. ABSOLUTE MAXIMUM RATINGS OPERATING RANGES. Environmental Ranges Electrical Ranges ELECTRICAL CHARACTERISTICS Transmission Characteristics. Attenuation Distortion Group Delay Distortion Gain Linearity. Total Distortion Including Quantizing Distortion Discrimination Against Out-of-Band Input Signals Discrimination Against 12- and 16-kHz Metering Signals Spurious Out-of-Band Signals at the Analog Output Overload Compression SWITCHING CHARACTERISTICS. SWITCHING WAVEFORMS OPERATING THE QLSLAC DEVICE. Power-Up Sequence Channel Enable EC Register SLIC Device Control and Data Lines Clock Mode Operation E1 Multiplex Operation Debounce Filters Operation Real-Time Data Register Operation Interrupt Mask Register Active State Inactive State Chopper Clock Reset States SIGNAL PROCESSING Zarlink Semiconductor Inc. Le58QL02/021/031 Data Sheet Overview of Digital Filters Two-Wire Impedance Matching Frequency Response Correction and Equalization Transhybrid Balancing Gain Adjustment Transmit Signal Processing Transmit PCM Interface Receive Signal Processing Receive PCM Interface Analog Impedance Scaling Network AISN Speech Coding Signaling on the PCM Highway Robbed-Bit Signaling Compatibility Default Filter Coefficients. COMMAND DESCRIPTION AND FORMATS Command Field Summary Microprocessor Interface Description SUMMARY OF MPI COMMANDS PROGRAMMABLE FILTERS General Description of CSD Coefficients. User Test States and Operating Conditions A-Law and µ-Law Companding APPLICATIONS Controlling the SLIC Device. Calculating Coefficients with WinSLAC Software Zarlink Semiconductor Inc. Le58QL02/021/031 Data Sheet APPLICATION CIRCUIT. LINE CARD PARTS LIST PHYSICAL DIMENSIONS. 32-Pin PLCC 44-Pin PLCC 44-Pin TQFP Zarlink Semiconductor Inc. Le58QL02/021/031 Data Sheet LIST OF FIGURES Figure Le58QL02JC 44-Pin PLCC Figure Le58QL021JC 44-Pin PLCC Figure Le58QL031JC 32-Pin PLCC Figure Le58QL021VC 44-Pin PLCC Figure Transmit Path Attenuation vs. Frequency Figure Receive Path Attenuation vs. Frequency Figure Group Delay Distortion Figure A-law Gain Linearity with Tone Input Both Paths . Figure µ-law Gain Linearity with Tone Input Both Paths . Figure Total Distortion with Tone Input Both Paths . Figure Discrimination Against Out-of-Band Signals Figure Spurious Out-of-Band Signals Figure Analog-to-Analog Overload Compression Figure Input and Output Waveforms for AC Tests Figure Microprocessor Interface Input Mode Figure Microprocessor Interface Output Mode Figure PCM Highway Timing for XE = 0 Transmit on Negative PCLK Edge Figure PCM Highway Timing for XE = 1 Transmit on Positive PCLK Edge Figure Master Clock Timing Figure Clock Mode Options. Figure SLIC Device I/O E1 Multiplex and Real-Time Data Register Operation. Figure E1 Multiplex Internal Timing Figure MPI Real-Time Data Register Figure QLSLAC Device Transmission Block Diagram Figure Robbed-Bit Frame Figure Le7920 SLIC/QLSLAC Device Application Circuit LIST OF TABLES Table QLSLAC Device Configurations 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR Channel Parameters Channel Monitors Global Chip Parameters Global Chip Status Monitors A-Law Positive Input Values. µ-Law Positive Input Values Zarlink Semiconductor Inc. Le58QL02/021/031 • Added "Packing" column and Note 2 to Ordering Information, on page 1 • Modified GAISN specification in Electrical Characteristics, on page • Enhanced format of package drawings in Physical Dimensions, on page 62 • Added new headers/footers due to Zarlink purchase of Legerity on August 3, • Modified the content in Package Assembly, on page 12 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries collectively “Zarlink” is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and unless agreed by Zarlink in writing may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE

PDF Datasheet Preview

Le58QL02/021/031

Quad Low Voltage Subscriber Line Audio-Processing Circuit VE580 Series
- Codec function on telephone switch line cards
- Low-power, V CMOS technology with 5-V tolerant digital inputs
- Software and coefficient compatible to the Le79Q02/ 021/031 QSLAC device
- Performs the functions of four codec/filters - Software programmable:

SLIC device input impedance Transhybrid balance Transmit and receive gains Equalization frequency response Digital I/O pins Programmable debouncing on one input Time slot assigner Programmable clock slot and PCM transmit clock edge
options - Standard microprocessor interface - A-law, µ-law, or linear coding - Single or Dual PCM ports available

Up to 128 channels PCLK at MHz per PCM port Optional supervision on the PCM highway - or MHz master clock derived from MCLK or PCLK - Built-in test modes with loopback, tone generation, and µP access to PCM data - Mixed state analog and digital impedance scaling - Performance guaranteed over a 12 dB gain range - Real Time Data register with interrupt open drain or TTL output - Supports multiplexed SLIC device outputs - Broadcast state - 256 kHz or 293 kHz chopper clock for Legerity SLIC devices with switching regulator - Maximum channel bandwidth for V.90 modems

RELATED LITERATURE
- 080754 Le58QL061/063 QLSLAC Device Data Sheet - 080761 QSLAC to QLSLAC Device Design

Conversion Guide - 080758 QSLAC to QLSLAC Guide to New Designs
ORDERING INFORMATION

Device

Package Green 1

Packing2

Le58QL02FJC
44-pin PLCC

Tube

Le58QL021FJC
44-pin PLCC

Tube

Le58QL021BVC
44-pin TQFP

Tray

Le58QL031DJC
32-pin PLCC

Tube

The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment.
For delivery using a tape and reel packing system, add a "T" suffix to the OPN Ordering Part Number when placing an order.

The Le58QL02/021/031 Quad Low Voltage Subscriber Line Audio-Processing Circuit QLSLAC devices integrate the key functions of analog line cards into high-performance, veryprogrammable, four-channel codec-filter devices. The QLSLAC devices are based on the proven design of Legerity’s reliable SLAC device families. The advanced architecture of the QLSLAC devices implements four independent channels and employs digital filters to allow software control of transmission, thus providing a cost-effective solution for the audio-processing function of programmable line cards. The QLSLAC devices are software and coefficient compatible to the QSLAC devices.

Advanced submicron CMOS technology makes the Le58QL02/ 021/031 QLSLAC devices economical, with both the functionality and the low power consumption needed in line card designs to maximize line card density at minimum cost. When used with four Legerity SLIC devices, a QLSLAC device provides a complete software-configurable solution to the BORSCHT functions.

BLOCK DIAGRAM

Analog

VIN1 VOUT 1

VIN2 VOUT 2

VIN3 VOUT 3

VIN4 VOUT 4

VREF

SLIC

CD11 CD21

C31 C41 C51

CD12 CD22

C32 C42 C52 CD13 CD23 C33 C43 C53 CD14 CD24 C34 C44 C54

CHCLK

Signal Processing Channel 1 CH 1

Signal Processing Channel 2 CH 2

Signal Processing Channel 3 CH 3

Signal Processing Channel 4 CH 4

Clock &

Reference Circuits

Time Slot Assigner TSA

SLIC Interface

Microprocessor Interface MPI

INT CS DIO DCLK Microprocessor

Dual/Single PCM

Highway DXA DRA TSCA DXB DRB TSCB

FS PCLK MCLK/E1

Document ID# 080753 Date April 09, 2009

Version:

Distribution Public Document

Le58QL02/021/031

Data Sheet

TABLE OF CONTENTS
ORDERING INFORMATION.

RELATED LITERATURE

BLOCK DIAGRAM

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

PRODUCT DESCRIPTION

BLOCK DESCRIPTIONS Clock and Reference Circuits Microprocessor Interface MPI Time Slot Assigner TSA Signal Processing Channels CHx SLIC Device Interface SLI

CONNECTION DIAGRAMS

PIN DESCRIPTIONS.

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES. Environmental Ranges Electrical Ranges

ELECTRICAL CHARACTERISTICS Transmission Characteristics. Attenuation Distortion Group Delay Distortion Gain Linearity. Total Distortion Including Quantizing Distortion Discrimination Against Out-of-Band Input Signals Discrimination Against 12- and 16-kHz Metering Signals Spurious Out-of-Band Signals at the Analog Output Overload Compression

SWITCHING CHARACTERISTICS.

SWITCHING WAVEFORMS

OPERATING THE QLSLAC DEVICE. Power-Up Sequence Channel Enable EC Register SLIC Device Control and Data Lines Clock Mode Operation E1 Multiplex Operation Debounce Filters Operation Real-Time Data Register Operation Interrupt Mask Register Active State Inactive State Chopper Clock Reset States

SIGNAL PROCESSING

Zarlink Semiconductor Inc.

Le58QL02/021/031

Data Sheet

Overview of Digital Filters Two-Wire Impedance Matching Frequency Response Correction and Equalization Transhybrid Balancing Gain Adjustment Transmit Signal Processing Transmit PCM Interface Receive Signal Processing Receive PCM Interface Analog Impedance Scaling Network AISN Speech Coding Signaling on the PCM Highway Robbed-Bit Signaling Compatibility Default Filter Coefficients.

COMMAND DESCRIPTION AND FORMATS Command Field Summary Microprocessor Interface Description

SUMMARY OF MPI COMMANDS

PROGRAMMABLE FILTERS General Description of CSD Coefficients. User Test States and Operating Conditions A-Law and µ-Law Companding

APPLICATIONS Controlling the SLIC Device. Calculating Coefficients with WinSLAC Software

Zarlink Semiconductor Inc.

Le58QL02/021/031

Data Sheet

APPLICATION CIRCUIT.

LINE CARD PARTS LIST

PHYSICAL DIMENSIONS. 32-Pin PLCC 44-Pin PLCC 44-Pin TQFP

Zarlink Semiconductor Inc.

Le58QL02/021/031

Data Sheet

LIST OF FIGURES

Figure Le58QL02JC 44-Pin PLCC Figure Le58QL021JC 44-Pin PLCC Figure Le58QL031JC 32-Pin PLCC Figure Le58QL021VC 44-Pin PLCC Figure Transmit Path Attenuation vs. Frequency Figure Receive Path Attenuation vs. Frequency Figure Group Delay Distortion Figure A-law Gain Linearity with Tone Input Both Paths . Figure µ-law Gain Linearity with Tone Input Both Paths . Figure Total Distortion with Tone Input Both Paths . Figure Discrimination Against Out-of-Band Signals Figure Spurious Out-of-Band Signals Figure Analog-to-Analog Overload Compression Figure Input and Output Waveforms for AC Tests Figure Microprocessor Interface Input Mode Figure Microprocessor Interface Output Mode Figure PCM Highway Timing for XE = 0 Transmit on Negative PCLK Edge Figure PCM Highway Timing for XE = 1 Transmit on Positive PCLK Edge Figure Master Clock Timing Figure Clock Mode Options. Figure SLIC Device I/O E1 Multiplex and Real-Time Data Register Operation. Figure E1 Multiplex Internal Timing Figure MPI Real-Time Data Register Figure QLSLAC Device Transmission Block Diagram Figure Robbed-Bit Frame Figure Le7920 SLIC/QLSLAC Device Application Circuit

LIST OF TABLES

Table

QLSLAC Device Configurations 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR Channel Parameters Channel Monitors Global Chip Parameters Global Chip Status Monitors A-Law Positive Input Values. µ-Law Positive Input Values

Zarlink Semiconductor Inc.

Le58QL02/021/031
• Added "Packing" column and Note 2 to Ordering Information, on page 1
• Modified GAISN specification in Electrical Characteristics, on page
• Enhanced format of package drawings in Physical Dimensions, on page 62
• Added new headers/footers due to Zarlink purchase of Legerity on August 3,
• Modified the content in Package Assembly, on page 12

Zarlink Semiconductor Inc.

For more information about all Zarlink products visit our Web Site at

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries collectively “Zarlink” is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.

This publication is issued to provide information only and unless agreed by Zarlink in writing may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.

Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc.

TECHNICAL DOCUMENTATION - NOT FOR RESALE

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived LE58QL021BVC Datasheet file may be downloaded here without warranties.

Datasheet ID: LE58QL021BVC 648973