KMPC8379CVRALG

KMPC8379CVRALG Datasheet

Part	Datasheet
KMPC8379CVRALG	KMPC8379CVRALG (pdf)

Related Parts	Information
KMPC8379VRALG	KMPC8379VRALG
KMPC8379ECVRALG	KMPC8379ECVRALG
KMPC8379EVRALG	KMPC8379EVRALG

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Freescale Semiconductor Technical Data MPC8379E PowerQUICC II Pro Processor Hardware Specifications This document provides an overview of the MPC8379E PowerQUICC II Pro processor features, including a block diagram showing the major functional components. This chip is a cost-effective, low-power, highly integrated host processor that addresses the requirements of several printing and imaging, consumer, and industrial applications, including main CPUs and I/O processors in printing systems, networking switches and line cards, wireless LANs WLANs , network access servers NAS , VPN routers, intelligent NIC, and industrial controllers. This chip extends the PowerQUICC family, adding higher CPU performance, additional functionality, and faster interfaces while addressing the requirements related to time-to-market, price, power consumption, and package size. This chip incorporates the e300c4s core, which includes 32 KB of L1 instruction and data caches and on-chip memory management units MMUs . The device offers two enhanced three-speed 10, 100, 1000 Mbps Ethernet interfaces, a DDR1/DDR2 SDRAM memory controller, a flexible, a 32-bit local bus controller, a 32-bit PCI controller, an optional dedicated security engine, a USB dual-role controller, a programmable interrupt Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2008-2012 Freescale Semiconductor, Inc. All rights reserved. controller, dual I2C controllers, a 4-channel DMA controller, an enhanced secured digital host controller, and a general-purpose I/O port. This figure shows the block diagram of the chip. Security DUART Dual I2C Timers GPIO SPI Interrupt Controller MPC8379E e300 Core 32 KB D-Cache 32 KB I-Cache Enhanced Local Bus DDR1/DDR2 SDRAM Controller USB Hi-Speed eTSEC eTSEC SATA SD/MMC Controller Host Device RGMII, RMII, RGMII, RMII, RTBI, MII RTBI, MII Figure MPC8379E Block Diagram and Features The following features are supported in the chip • e300c4s core built on Power technology with 32 KB instruction cache and 32 KB data cache, a floating point unit, and two integer units • DDR1/DDR2 memory controller supporting a 32/64-bit interface • Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MHz operation • 32-bit local bus interface running up to 133-MHz • USB full/high speed support • Power management controller for low-power consumption • High degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration • Optional security engine provides acceleration for control and data plane security protocols The optional security engine SEC is noted with the extension “E” at the end. It allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms. Freescale Semiconductor In addition to the security engine, a new high-speed interface such as SATA, is included. This table compares the differences between MPC837xE derivatives and provides the number of ports available for each interface. Table High-Speed Interfaces on the MPC8377E, MPC8378E, and MPC8379E Descriptions MPC8377E MPC8378E MPC8379E SGMII SATA DDR Memory Controller The DDR1/DDR2 memory controller includes the following features • Single 32- or 64-bit interface supporting both DDR1 and DDR2 SDRAM • Support for up to 400-MHz data rate • Support up to 4 chip selects • 64-Mbit to 2-Gbit for DDR1 and to 4-Gbit for DDR2 devices with x8/x16/x32 data ports no direct x4 support • Support for up to 32 simultaneous open pages • Supports auto refresh • On-the-fly power management using CKE • 1.8-/2.5-V SSTL2 compatible I/O USB Dual-Role Controller Freescale Semiconductor Dual Enhanced Three-Speed Ethernet Controllers eTSECs The eTSECs include the following features • Two enhanced Ethernet interfaces can be used for RGMII/MII/RMII/RTBI • Two controllers conform to IEEE Std IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588 standards • Support for Wake-on-Magic Packet , a method to bring the device from standby to full operating mode • MII management interface for external PHY control and status Integrated Programmable Interrupt Controller IPIC The integrated programmable interrupt controller IPIC implements the necessary functions to provide a flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller. The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. During the power ramp up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of time that all input and output pins will actively be driven and cause contention and excessive current. To avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltages VDD and AVDD before the I/O voltages and assert PORESET before the power supplies fully ramp up. VDD and AVDD must reach 90% of their nominal value before GVDD, LVDD, and OVDD reach 10% of their value, see the following figure. I/O voltage LVDD, and not have any ordering requirements with respect to one another. I/O Voltage GVDD, LVDD, and OVDD Core Voltage VDD, AVDD Figure Power-Up Sequencing Example Note that the SerDes power supply L[1,2]_nVDD should follow the same timing as the core supply VDD . The device does not require the core supply voltage and I/O supply voltages to be powered down in any particular order. 3 Power Characteristics The estimated typical power dissipation for the chip device is shown in this table. Table Power Dissipation 1 Core Frequency CSB/DDR Frequency Sleep Power Typical Application Typical Application Max Application at Tj = 65°C W 2 at Tj = 65°C W 2 at Tj = 125°C W 3 at Tj = 125°C W 4 Freescale Semiconductor Table Power Dissipation 1 continued Core Frequency CSB/DDR Frequency Sleep Power Typical Application Typical Application Max Application at Tj = 65°C W 2 at Tj = 65°C W 2 at Tj = 125°C W 3 at Tj = 125°C W 4 The values do not include I/O supply power OVDD, LVDD, GVDD or AVDD. For I/O power values, see Table Typical power is based on a voltage of VDD = V for core frequencies 667 MHz or VDD = V for core frequencies of 800 MHz, and running a Dhrystone benchmark application. Typical power is based on a voltage of VDD = V for core frequencies 667 MHz or VDD = V for core frequencies of 800 MHz, and running a Dhrystone benchmark application. Maximum power is based on a voltage of VDD = V for core frequencies 667 MHz or VDD = V for core frequencies of 800 MHz, worst case process, and running an artificial smoke test. Freescale Semiconductor This table shows the estimated typical I/O power dissipation for the device. Table Typical I/O Power Dissipation Interface Parameter 200 MHz data rate, 32-bit 200 MHz data rate, 64-bit 266 MHz data rate, 32-bit 266 MHz data rate, 64-bit DDR I/O 65% utilization 2 pair of clocks 300 MHz data rate, 32-bit 300 MHz data rate, 64-bit 333 MHz data rate, 32-bit 333 MHz data rate, 64-bit 400 MHz data rate, 32-bit 400 MHz data rate, 64-bit PCI I/O Load = 30 pf 33 MHz, 32-bit 66 MHz, 32-bit 167 MHz, 32-bit Local Bus I/O Load = 25 pf 133 MHz, 32-bit 83 MHz, 32-bit 25 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Section “Part Numbers Fully Addressed by This Document.” Freescale Semiconductor Part Numbers Fully Addressed by This Document Table Part Numbering Nomenclature MPC 8379 E Product Code Part Identifier Encryption Acceleratio Temperature Range 1 Package 2 e300 core Frequency 3 Data Rate 8379 Blank = Not included E = included Blank = 0°C Ta to 125°C Tj C = Ta to 125°C Tj VR = Pb-free AN = 800 MHz G = 400 MHz 689 TePBGA II AL = 667 MHz F = 333 MHz AJ = 533 MHz D = 266 MHz AG = 400 MHz Blank = Freescale ATMC fab A= GlobalFoundries fab Note 1 Contact local Freescale office on availability of parts with an extended temperature range. 2 See Section 21, “Package and Pin Listings,” for more information on the available package type. 3 Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this This table lists the available core and DDR data rate frequency combinations. Table Available Parts Core/DDR Data Rate MPC8377E 800 MHz/400 MHz 667 MHz/400 MHz 533 MHz/333 MHz 400 MHz/266 MHz MPC8378E 800 MHz/400 MHz 667 MHz/400 MHz 533 MHz/333 MHz 400 MHz/266 MHz MPC8379E 800 MHz/400 MHz 667 MHz/400 MHz 533 MHz/333 MHz 400 MHz/266 MHz Freescale Semiconductor This table shows the SVR and PVR settings by device. Device MPC8377 MPC8377E MPC8378 MPC8378E MPC8379 MPC8379E Package TePBGA II 0x80C7_0010 0x80C6_0010 0x80C5_0010 0x80C4_0010 0x80C3_0010 0x80C2_0010 0x80C7_0021 0x80C6_0021 0x80C5_0021 0x80C4_0021 0x80C3_0021 0x80C2_0021 0x8086_1010 0x8086_1011 Part Marking Parts are marked as in the example as shown in this figure. MPCnnnnetppaaar core/platform MHZ ATWLYYWW YWWLAZ

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Freescale Semiconductor

Technical Data

MPC8379E PowerQUICC II Pro Processor Hardware Specifications

This document provides an overview of the MPC8379E PowerQUICC II Pro processor features, including a block diagram showing the major functional components. This chip is a cost-effective, low-power, highly integrated host processor that addresses the requirements of several printing and imaging, consumer, and industrial applications, including main CPUs and I/O processors in printing systems, networking switches and line cards, wireless LANs WLANs , network access servers NAS , VPN routers, intelligent NIC, and industrial controllers. This chip extends the PowerQUICC family, adding higher CPU performance, additional functionality, and faster interfaces while addressing the requirements related to time-to-market, price, power consumption, and package size.

This chip incorporates the e300c4s core, which includes 32 KB of L1 instruction and data caches and on-chip memory management units MMUs . The device offers two enhanced three-speed 10, 100, 1000 Mbps Ethernet interfaces, a DDR1/DDR2 SDRAM memory controller, a flexible, a 32-bit local bus controller, a 32-bit PCI controller, an optional dedicated security engine, a USB dual-role controller, a programmable interrupt
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
2008-2012 Freescale Semiconductor, Inc. All rights reserved.
controller, dual I2C controllers, a 4-channel DMA controller, an enhanced secured digital host controller, and a general-purpose I/O port. This figure shows the block diagram of the chip.

Security

DUART Dual I2C Timers

GPIO SPI Interrupt Controller

MPC8379E
e300 Core
32 KB D-Cache
32 KB I-Cache

Enhanced Local Bus

DDR1/DDR2 SDRAM Controller

USB Hi-Speed
eTSEC
eTSEC

SATA

SD/MMC Controller

Host Device

RGMII, RMII, RGMII, RMII,

RTBI, MII

RTBI, MII

Figure MPC8379E Block Diagram and Features

The following features are supported in the chip
• e300c4s core built on Power technology with 32 KB instruction cache and 32 KB data cache, a floating point unit, and two integer units
• DDR1/DDR2 memory controller supporting a 32/64-bit interface
• Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MHz operation
• 32-bit local bus interface running up to 133-MHz
• USB full/high speed support
• Power management controller for low-power consumption
• High degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration
• Optional security engine provides acceleration for control and data plane security protocols

The optional security engine SEC is noted with the extension “E” at the end. It allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.

Freescale Semiconductor

In addition to the security engine, a new high-speed interface such as SATA, is included. This table compares the differences between MPC837xE derivatives and provides the number of ports available for each interface.

Table High-Speed Interfaces on the MPC8377E, MPC8378E, and MPC8379E

Descriptions

MPC8377E

MPC8378E

MPC8379E

SGMII

SATA

DDR Memory Controller

The DDR1/DDR2 memory controller includes the following features
• Single 32- or 64-bit interface supporting both DDR1 and DDR2 SDRAM
• Support for up to 400-MHz data rate
• Support up to 4 chip selects
• 64-Mbit to 2-Gbit for DDR1 and to 4-Gbit for DDR2 devices with x8/x16/x32 data ports no direct x4 support
• Support for up to 32 simultaneous open pages
• Supports auto refresh
• On-the-fly power management using CKE
• 1.8-/2.5-V SSTL2 compatible I/O

USB Dual-Role Controller

Freescale Semiconductor

Dual Enhanced Three-Speed Ethernet Controllers eTSECs

The eTSECs include the following features
• Two enhanced Ethernet interfaces can be used for RGMII/MII/RMII/RTBI
• Two controllers conform to IEEE Std IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588 standards
• Support for Wake-on-Magic Packet , a method to bring the device from standby to full operating mode
• MII management interface for external PHY control and status

Integrated Programmable Interrupt Controller IPIC

The integrated programmable interrupt controller IPIC implements the necessary functions to provide a flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller.
The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. During the power ramp up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of time that all input and output pins will actively be driven and cause contention and excessive current. To avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltages VDD and AVDD before the I/O voltages and assert PORESET before the power supplies fully ramp up. VDD and AVDD must reach 90% of their nominal value before GVDD, LVDD, and OVDD reach 10% of their value, see the following figure. I/O voltage LVDD, and not have any ordering requirements with respect to one another.

I/O Voltage GVDD, LVDD, and OVDD

Core Voltage VDD, AVDD

Figure Power-Up Sequencing Example

Note that the SerDes power supply L[1,2]_nVDD should follow the same timing as the core supply VDD .

The device does not require the core supply voltage and I/O supply voltages to be powered down in any particular order.
3 Power Characteristics

The estimated typical power dissipation for the chip device is shown in this table.

Table Power Dissipation 1

Core Frequency CSB/DDR Frequency Sleep Power Typical Application Typical Application Max Application
at Tj = 65°C W 2 at Tj = 65°C W 2 at Tj = 125°C W 3 at Tj = 125°C W 4

Freescale Semiconductor

Table Power Dissipation 1 continued

Core Frequency CSB/DDR Frequency Sleep Power Typical Application Typical Application Max Application
at Tj = 65°C W 2 at Tj = 65°C W 2 at Tj = 125°C W 3 at Tj = 125°C W 4

The values do not include I/O supply power OVDD, LVDD, GVDD or AVDD. For I/O power values, see Table Typical power is based on a voltage of VDD = V for core frequencies 667 MHz or VDD = V for core frequencies of
800 MHz, and running a Dhrystone benchmark application.

Typical power is based on a voltage of VDD = V for core frequencies 667 MHz or VDD = V for core frequencies of 800 MHz, and running a Dhrystone benchmark application.

Maximum power is based on a voltage of VDD = V for core frequencies 667 MHz or VDD = V for core frequencies of 800 MHz, worst case process, and running an artificial smoke test.

Freescale Semiconductor

This table shows the estimated typical I/O power dissipation for the device.

Table Typical I/O Power Dissipation

Interface Parameter
200 MHz data rate, 32-bit
200 MHz data rate, 64-bit
266 MHz data rate, 32-bit
266 MHz data rate, 64-bit

DDR I/O 65% utilization 2 pair of clocks
300 MHz data rate, 32-bit
300 MHz data rate, 64-bit
333 MHz data rate, 32-bit
333 MHz data rate, 64-bit
400 MHz data rate, 32-bit
400 MHz data rate, 64-bit

PCI I/O Load = 30 pf
33 MHz, 32-bit
66 MHz, 32-bit
167 MHz, 32-bit

Local Bus I/O Load = 25 pf
133 MHz, 32-bit
83 MHz, 32-bit
25 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section “Part Numbers Fully Addressed by This Document.”

Freescale Semiconductor

Part Numbers Fully Addressed by This Document

Table Part Numbering Nomenclature

MPC 8379 E

Product Code

Part Identifier

Encryption Acceleratio

Temperature Range 1

Package 2
e300 core

Frequency 3 Data Rate
8379

Blank = Not included

E = included

Blank = 0°C Ta to 125°C Tj C = Ta to 125°C Tj

VR = Pb-free AN = 800 MHz G = 400 MHz 689 TePBGA II AL = 667 MHz F = 333 MHz

AJ = 533 MHz D = 266 MHz AG = 400 MHz

Blank = Freescale ATMC fab

A= GlobalFoundries fab

Note 1 Contact local Freescale office on availability of parts with an extended temperature range. 2 See Section 21, “Package and Pin Listings,” for more information on the available package type. 3 Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this

This table lists the available core and DDR data rate frequency combinations.

Table Available Parts Core/DDR Data Rate

MPC8377E 800 MHz/400 MHz 667 MHz/400 MHz 533 MHz/333 MHz 400 MHz/266 MHz

MPC8378E 800 MHz/400 MHz 667 MHz/400 MHz 533 MHz/333 MHz 400 MHz/266 MHz

MPC8379E 800 MHz/400 MHz 667 MHz/400 MHz 533 MHz/333 MHz 400 MHz/266 MHz

Freescale Semiconductor

This table shows the SVR and PVR settings by device.

Device

MPC8377 MPC8377E MPC8378 MPC8378E MPC8379 MPC8379E

Package TePBGA II
0x80C7_0010 0x80C6_0010 0x80C5_0010 0x80C4_0010 0x80C3_0010 0x80C2_0010
0x80C7_0021 0x80C6_0021 0x80C5_0021 0x80C4_0021 0x80C3_0021 0x80C2_0021
0x8086_1010
0x8086_1011

Part Marking

Parts are marked as in the example as shown in this figure.

MPCnnnnetppaaar
core/platform MHZ

ATWLYYWW

YWWLAZ

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Datasheet ID: KMPC8379CVRALG 635550