LE58083ABGC

LE58083ABGC Datasheet

Le58083

Part	Datasheet
LE58083ABGC	LE58083ABGC (pdf)

Related Parts	Information
LE58083ABGCT	LE58083ABGCT

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Le58083 Low Voltage Subscriber Line Audio-processing Circuit VE580 Series • Codec function on telephone switch line cards • Low-power, V CMOS technology with 5 V tolerant digital inputs • Pin programmable PCM/MPI or GCI interface • Software and coefficient compatible to the VE580 series QLSLAC devices • Standard PCM/microprocessor interface PCM/MPI mode Single or Dual PCM ports available Time slot assigner up to 128 channels per port Clock slot and transmit clock edge options Optional supervision on the PCM highway or MHz master clock derived from MCLK or PCLK µP access to PCM data Real Time Data with interrupt open drain or TTL Broadcast mode • General Circuit Interface GCI mode Control and PCM data on a single port Mbits/s data rate MHz or MHz clock option • Performs the functions of eight codec/filters • Software programmable SLIC device input impedance and Transhybrid balance Transmit and receive gains and Equalization Programmable Digital I/O pins with debouncing • A-law, µ-law, or linear coding • Built-in test modes with loopback, tone generation, and µP access to PCM data • Mixed state analog and digital impedance scaling • Performance guaranteed over a 12 dB gain range • Supports multiplexed SLIC device outputs • 256 kHz or 293 kHz chopper clock for Zarlink SLIC devices with switching regulator • Maximum channel bandwidth for V.90 modems ORDERING INFORMATION Device Package Le58083ABGC 121-pin BGA Green package * *Green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. RELATED LITERATURE • 080753 Le58QL02/021/031 QLSLAC Data Sheet • 080754 Le58QL061/063 QLSLAC Data Sheet • 080761 QSLAC to QLSLAC Design Conversion Guide • 080758 QSLAC to QLSLAC Guide to New Designs DESCRIPTION The Le58083 Octal Low Voltage Subscriber Line AudioProcessing Circuit Octal SLAC devices integrate the key functions of analog line cards into high-performance, veryprogrammable, eight-channel codec-filter devices. The Le58083 Octal SLAC devices are based on the proven design of Zarlink’s reliable SLAC device families. The advanced architecture of the Le58083 Octal SLAC devices implements eight independent channels and employs digital filters to allow software control of transmission, thus providing a cost-effective solution for the audio-processing function of programmable line cards. The Le58083 Octal SLAC devices are software and coefficient compatible to the VE580 series QLSLAC devices. Advanced submicron CMOS technology makes the Le58083 Octal SLAC devices economical, with both the functionality and the low power consumption needed in line card designs to maximize line card density at minimum cost. When used with multiple Zarlink SLIC devices, an Le58083 Octal SLAC device provides a complete software-configurable solution to the BORSCHT functions. BLOCK DIAGRAM ANALOG VIN 1-8 VOUT 1-8 VREF_1, VREF_2 SLIC CONTROLS CD1 1-8 CD2 1-8 C3 1-8 C4 1-8 C5 1-8 C6 1-8 C7 1-8 Signal Processing Channels 1-8 PCM & GCI Interface & Time Slot Assigner TSA GCI/PCM Interface DXA/DU DRA/DD TSCA DXB DRB TSCB SLIC Interface Clock & Reference Circuits FS/FSC PCLK/DCL MCLK_1, MCLK_2 GCI Control Logic & Microprocessor Interface DCLK-S0_1, DCLK-SO_2 CS/PG_1, CS/PG_2 DIO-S1_1, DIO-S1_2 INT_1, INT_2 RST Document ID# 080921 Date Sep 18, 2007 E Version: Distribution Public Document Le58083 Data Sheet TABLE OF CONTENTS Applications Features Related Literature Ordering Information Description. Block Diagram List of Figures List of Tables Product Description Device Description Block Descriptions Clock and Reference Circuits Microprocessor Interface MPI Time Slot Assigner TSA Signal Processing Channels CHx SLIC Device Interface SLI Connection Diagram 121-Pin BGA Pin Descriptions Absolute Maximum Ratings Operating Ranges Environmental Ranges Electrical Ranges Electrical Characteristics Transmission Characteristics. Attenuation Distortion Group Delay Distortion Gain Linearity. Total Distortion Including Quantizing Distortion Discrimination Against Out-of-Band Input Signals Discrimination Against 12- and 16-kHz Metering Signals Spurious Out-of-Band Signals at the Analog Output Overload Compression Switching Characteristics. Switching Waveforms GCI Timing Specifications GCI Waveforms Operating the Le58083 Octal SLAC Device. Power-Up Sequence PCM and GCI State Selection Channel Enable EC Register PCM/MPI Mode SLIC Device Control and Data Lines Clock Mode Operation E1 Multiplex Operation Debounce Filters Operation Real-Time Data Register Operation Interrupt Mask Register Active State Inactive State Chopper Clock Reset States Signal Processing Overview of Digital Filters Two-Wire Impedance Matching Frequency Response Correction and Equalization Zarlink Semiconductor Inc. Le58083 Data Sheet Zarlink Semiconductor Inc. Le58083 Data Sheet Summary of Monitor Channel Commands GCI Commands TOP Transfer Operation Command SOP Status Operation Command SOP Control Byte Command Format COP Coefficient Operation Command Details of COP, CSD Data Commands Programmable Filters General Description of CSD Coefficients. User Test States and Operating Conditions A-Law and µ-Law Companding Applications Application Circuit. Line card parts List Physical Dimensions. LIST OF FIGURES Figure Transmit Path Attenuation vs. Frequency Figure Receive Path Attenuation vs. Frequency Figure Group Delay Distortion Figure A-law Gain Linearity with Tone Input Both Paths Figure µ-law Gain Linearity with Tone Input Both Paths Figure Total Distortion with Tone Input Both Paths Figure Discrimination Against Out-of-Band Signals Figure Spurious Out-of-Band Signals. Figure Analog-to-Analog Overload Compression. Figure Input and Output Waveforms for AC Tests Figure Microprocessor Interface Input Mode Figure Microprocessor Interface Output Mode . Figure PCM Highway Timing for XE = 0 Transmit on Negative PCLK Edge Figure PCM Highway Timing for XE = 1 Transmit on Positive PCLK Edge Figure Double PCLK PCM Timing Figure Master Clock Timing Figure MHz DCL Operation Figure MHz DCL Operation Figure Clock Mode Options PCM/MPI Mode Figure SLIC Device I/O, E1 Multiplex and Real-Time Data Register Operation. Figure E1 Multiplex Internal Timing Figure MPI Real-Time Data Register Figure Le58083 Octal SLAC Transmission Block Diagram Figure Robbed-Bit Frame Figure Time Slot Control and GCI Interface Figure Multiplexed GCI Time Slot Structure Figure Security Procedure for C/I Downstream Bytes Figure Maximum Speed Monitor Handshake Timing Figure Monitor Transmitter Mode Diagram. Figure Monitor Receiver State Diagram Figure Le57D11 SLIC/Le58083 Octal SLAC Application Circuit Zarlink Semiconductor Inc. Le58083 Data Sheet LIST OF TABLES Table Le58083 Octal SLAC Device Pin Names and Numbers Table 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR Table PCM/GCI Mode Selection Table Channel Parameters. Table Channel Monitors Table Global Chip Parameters Table Global Chip Status Monitors. Table GCI Channel Assignment Codes Table Generic Byte Transmission Sequence Table Byte Transmission Sequence for TOP Command Table General Transmission Sequence of SOP Command Table Generic Transmission Sequence for COP Command Table A-Law Positive Input Values Table µ-Law Positive Input Values Zarlink Semiconductor Inc. Le58083 Data Sheet PRODUCT DESCRIPTION The Le58083 Octal SLAC device performs the codec/filter and two-to-four-wire conversion functions required of the subscriber line interface circuitry in telecommunications equipment. These functions involve converting audio signals into digital PCM samples and converting digital PCM samples back into audio signals. During conversion, digital filters are used to band limit the voice signals. All of the digital filtering is performed in digital signal processors operating from a master clock, which can be derived either from PCLK or MCLK in the PCM/MPI mode and DCL in the GCI mode. The Le58083 Octal SLAC device is configured as two four-channel groups that share a common reset and PCM/GCI interface. Each four-channel group has its own chip select for individual programming. The signal names for each four-channel SLAC device are differentiated by _1 or Generic naming of each signal is C_X, where the subscript C equals the channel number 1 through 4 and the _X equals the four-channel group number 1 or For example, VIN3_2 would identify channel 3 of the second four-channel group. Eight independent channels allow the Le58083 Octal SLAC device to function as eight SLAC devices. In PCM/MPI mode, each channel has its own enable bit EC1, EC2, EC3, etc. to allow individual channel programming. If more than one Channel Enable bit is High or if all Channel Enable bits are High, all channels enabled will receive the programming information written therefore, a Broadcast mode can be implemented by simply enabling all channels in the device to receive the information and enabling both chip selects. The Channel Enable bits are contained in the Channel Enable EC register, which is written and read using Commands 4A/4Bh. The Broadcast mode is useful in initializing Le58083 Octal SLAC devices in a large system. In GCI mode, one GCI channel controls two channels of the Le58083 Octal SLAC device. The Monitor channel and SC channel within the GCI channel are used to read/write filter coefficient data, read/write operating conditions and to read/write data to/from the programmable I/O ports of the two channels. Two pairs of GCI channels control the two four-channel groups in the Le58083 Octal SLAC device. The four GCI channels used, of the eight total available, are determined by S0 and S1 inputs. The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment of the two-wire termination impedance, and provide equalization of the receive and transmit paths. All programmable digital filter coefficients can be calculated using the WinSLAC software. In PCM/MPI mode, Data transmitted or received on the PCM highway can be 8-bit companded code with an optional 8-bit signaling byte in the transmit direction or 16-bit linear code. The 8-bit codes appear 1 byte per time slot, while the 16-bit code appears in two consecutive time slots. The compressed PCM codes can be either 8-bit companded A-law or µ-law. The PCM data is read from and written to the PCM highway in user-programmable time slots at rates of 128 kHz to MHz. The transmit clock edge and clock slot can be selected for compatibility with other devices that can be connected to the PCM highway. In GCI mode, two 8-bit companded codes are received or transmitted per GCI channel. The compressed PCM codes can be either 8-bit companded A-law or µ-law. There is no Signaling or Linear mode available when GCI mode is selected. The programming software is backward compatible to the Zarlink Le58000 SLAC family of devices. DEVICE DESCRIPTION PCM/GCI Highway Dual/single Programmable I/O per Channel Five I/O Two Output Chopper Clock Yes Package BGA Part Number Le58083GC BLOCK DESCRIPTIONS Clock and Reference Circuits This block generates a master clock and a frame sync signal for the digital circuits. It also generates an analog reference voltage for the analog circuits. Microprocessor Interface MPI • Removed standard non-green OPN from Ordering Information, on page 1 • Enhanced format of package drawing in Physical Dimensions, on page 93 • Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries collectively “Zarlink” is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and unless agreed by Zarlink in writing may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE

PDF Datasheet Preview

Le58083

Low Voltage Subscriber Line Audio-processing Circuit VE580 Series
• Codec function on telephone switch line cards
• Low-power, V CMOS technology with 5 V tolerant digital inputs
• Pin programmable PCM/MPI or GCI interface
• Software and coefficient compatible to the VE580
series QLSLAC devices
• Standard PCM/microprocessor interface

PCM/MPI mode

Single or Dual PCM ports available Time slot assigner up to 128 channels per port Clock slot and transmit clock edge options Optional supervision on the PCM highway
or MHz master clock derived from MCLK or PCLK µP access to PCM data Real Time Data with interrupt open drain or TTL Broadcast mode
• General Circuit Interface GCI mode Control and PCM data on a single port Mbits/s data rate MHz or MHz clock option
• Performs the functions of eight codec/filters
• Software programmable SLIC device input impedance and Transhybrid balance Transmit and receive gains and Equalization Programmable Digital I/O pins with debouncing
• A-law, µ-law, or linear coding
• Built-in test modes with loopback, tone generation, and µP access to PCM data
• Mixed state analog and digital impedance scaling
• Performance guaranteed over a 12 dB gain range
• Supports multiplexed SLIC device outputs
• 256 kHz or 293 kHz chopper clock for Zarlink SLIC devices with switching regulator
• Maximum channel bandwidth for V.90 modems
ORDERING INFORMATION

Device

Package

Le58083ABGC
121-pin BGA Green package *
*Green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment.

RELATED LITERATURE
• 080753 Le58QL02/021/031 QLSLAC Data Sheet
• 080754 Le58QL061/063 QLSLAC Data Sheet
• 080761 QSLAC to QLSLAC Design Conversion

Guide
• 080758 QSLAC to QLSLAC Guide to New Designs

DESCRIPTION The Le58083 Octal Low Voltage Subscriber Line AudioProcessing Circuit Octal SLAC devices integrate the key functions of analog line cards into high-performance, veryprogrammable, eight-channel codec-filter devices. The Le58083 Octal SLAC devices are based on the proven design of Zarlink’s reliable SLAC device families. The advanced architecture of the Le58083 Octal SLAC devices implements eight independent channels and employs digital filters to allow software control of transmission, thus providing a cost-effective solution for the audio-processing function of programmable line cards. The Le58083 Octal SLAC devices are software and coefficient compatible to the VE580 series QLSLAC devices.

Advanced submicron CMOS technology makes the Le58083 Octal SLAC devices economical, with both the functionality and the low power consumption needed in line card designs to maximize line card density at minimum cost. When used with multiple Zarlink SLIC devices, an Le58083 Octal SLAC device provides a complete software-configurable solution to the BORSCHT functions.

BLOCK DIAGRAM

ANALOG

VIN 1-8 VOUT 1-8

VREF_1, VREF_2 SLIC

CONTROLS CD1 1-8 CD2 1-8 C3 1-8 C4 1-8 C5 1-8 C6 1-8 C7 1-8

Signal Processing Channels 1-8

PCM & GCI Interface &

Time Slot Assigner TSA

GCI/PCM Interface

DXA/DU DRA/DD TSCA DXB DRB TSCB

SLIC Interface

Clock &

Reference Circuits

FS/FSC PCLK/DCL MCLK_1, MCLK_2

GCI Control Logic & Microprocessor Interface

DCLK-S0_1, DCLK-SO_2 CS/PG_1, CS/PG_2

DIO-S1_1, DIO-S1_2 INT_1, INT_2 RST

Document ID# 080921 Date Sep 18, 2007

E Version:

Distribution Public Document

Le58083

Data Sheet

TABLE OF CONTENTS
Applications Features Related Literature Ordering Information Description. Block Diagram List of Figures List of Tables Product Description Device Description Block Descriptions

Clock and Reference Circuits Microprocessor Interface MPI Time Slot Assigner TSA Signal Processing Channels CHx SLIC Device Interface SLI Connection Diagram 121-Pin BGA Pin Descriptions Absolute Maximum Ratings Operating Ranges Environmental Ranges Electrical Ranges Electrical Characteristics Transmission Characteristics. Attenuation Distortion Group Delay Distortion Gain Linearity. Total Distortion Including Quantizing Distortion Discrimination Against Out-of-Band Input Signals Discrimination Against 12- and 16-kHz Metering Signals Spurious Out-of-Band Signals at the Analog Output Overload Compression Switching Characteristics. Switching Waveforms GCI Timing Specifications GCI Waveforms Operating the Le58083 Octal SLAC Device. Power-Up Sequence PCM and GCI State Selection Channel Enable EC Register PCM/MPI Mode SLIC Device Control and Data Lines Clock Mode Operation E1 Multiplex Operation Debounce Filters Operation Real-Time Data Register Operation Interrupt Mask Register Active State Inactive State Chopper Clock Reset States Signal Processing Overview of Digital Filters Two-Wire Impedance Matching Frequency Response Correction and Equalization

Zarlink Semiconductor Inc.

Le58083

Data Sheet

Zarlink Semiconductor Inc.

Le58083

Data Sheet

Summary of Monitor Channel Commands GCI Commands TOP Transfer Operation Command SOP Status Operation Command SOP Control Byte Command Format COP Coefficient Operation Command Details of COP, CSD Data Commands

Programmable Filters General Description of CSD Coefficients. User Test States and Operating Conditions A-Law and µ-Law Companding

Applications Application Circuit. Line card parts List Physical Dimensions.

LIST OF FIGURES

Figure Transmit Path Attenuation vs. Frequency Figure Receive Path Attenuation vs. Frequency Figure Group Delay Distortion Figure A-law Gain Linearity with Tone Input Both Paths Figure µ-law Gain Linearity with Tone Input Both Paths Figure Total Distortion with Tone Input Both Paths Figure Discrimination Against Out-of-Band Signals Figure Spurious Out-of-Band Signals. Figure Analog-to-Analog Overload Compression. Figure Input and Output Waveforms for AC Tests Figure Microprocessor Interface Input Mode Figure Microprocessor Interface Output Mode . Figure PCM Highway Timing for XE = 0 Transmit on Negative PCLK Edge Figure PCM Highway Timing for XE = 1 Transmit on Positive PCLK Edge Figure Double PCLK PCM Timing Figure Master Clock Timing Figure MHz DCL Operation Figure MHz DCL Operation Figure Clock Mode Options PCM/MPI Mode Figure SLIC Device I/O, E1 Multiplex and Real-Time Data Register Operation. Figure E1 Multiplex Internal Timing Figure MPI Real-Time Data Register Figure Le58083 Octal SLAC Transmission Block Diagram Figure Robbed-Bit Frame Figure Time Slot Control and GCI Interface Figure Multiplexed GCI Time Slot Structure Figure Security Procedure for C/I Downstream Bytes Figure Maximum Speed Monitor Handshake Timing Figure Monitor Transmitter Mode Diagram. Figure Monitor Receiver State Diagram Figure Le57D11 SLIC/Le58083 Octal SLAC Application Circuit

Zarlink Semiconductor Inc.

Le58083

Data Sheet

LIST OF TABLES

Table Le58083 Octal SLAC Device Pin Names and Numbers Table 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR Table PCM/GCI Mode Selection Table Channel Parameters. Table Channel Monitors Table Global Chip Parameters Table Global Chip Status Monitors. Table GCI Channel Assignment Codes Table Generic Byte Transmission Sequence Table Byte Transmission Sequence for TOP Command Table General Transmission Sequence of SOP Command Table Generic Transmission Sequence for COP Command Table A-Law Positive Input Values Table µ-Law Positive Input Values

Zarlink Semiconductor Inc.

Le58083

Data Sheet

PRODUCT DESCRIPTION

The Le58083 Octal SLAC device performs the codec/filter and two-to-four-wire conversion functions required of the subscriber line interface circuitry in telecommunications equipment. These functions involve converting audio signals into digital PCM samples and converting digital PCM samples back into audio signals. During conversion, digital filters are used to band limit the voice signals. All of the digital filtering is performed in digital signal processors operating from a master clock, which can be derived either from PCLK or MCLK in the PCM/MPI mode and DCL in the GCI mode.

The Le58083 Octal SLAC device is configured as two four-channel groups that share a common reset and PCM/GCI interface. Each four-channel group has its own chip select for individual programming. The signal names for each four-channel SLAC device are differentiated by _1 or Generic naming of each signal is C_X, where the subscript C equals the channel number 1 through 4 and the _X equals the four-channel group number 1 or For example, VIN3_2 would identify channel 3 of the second four-channel group.

Eight independent channels allow the Le58083 Octal SLAC device to function as eight SLAC devices. In PCM/MPI mode, each channel has its own enable bit EC1, EC2, EC3, etc. to allow individual channel programming. If more than one Channel Enable bit is High or if all Channel Enable bits are High, all channels enabled will receive the programming information written therefore, a Broadcast mode can be implemented by simply enabling all channels in the device to receive the information and enabling both chip selects. The Channel Enable bits are contained in the Channel Enable EC register, which is written and read using Commands 4A/4Bh. The Broadcast mode is useful in initializing Le58083 Octal SLAC devices in a large system.

In GCI mode, one GCI channel controls two channels of the Le58083 Octal SLAC device. The Monitor channel and SC channel within the GCI channel are used to read/write filter coefficient data, read/write operating conditions and to read/write data to/from the programmable I/O ports of the two channels. Two pairs of GCI channels control the two four-channel groups in the Le58083 Octal SLAC device. The four GCI channels used, of the eight total available, are determined by S0 and S1 inputs.

The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment of the two-wire termination impedance, and provide equalization of the receive and transmit paths. All programmable digital filter coefficients can be calculated using the WinSLAC software.

In PCM/MPI mode, Data transmitted or received on the PCM highway can be 8-bit companded code with an optional 8-bit signaling byte in the transmit direction or 16-bit linear code. The 8-bit codes appear 1 byte per time slot, while the 16-bit code appears in two consecutive time slots. The compressed PCM codes can be either 8-bit companded A-law or µ-law. The PCM data is read from and written to the PCM highway in user-programmable time slots at rates of 128 kHz to MHz. The transmit clock edge and clock slot can be selected for compatibility with other devices that can be connected to the PCM highway.

In GCI mode, two 8-bit companded codes are received or transmitted per GCI channel. The compressed PCM codes can be either 8-bit companded A-law or µ-law. There is no Signaling or Linear mode available when GCI mode is selected.

The programming software is backward compatible to the Zarlink Le58000 SLAC family of devices.

DEVICE DESCRIPTION

PCM/GCI Highway Dual/single

Programmable I/O per Channel

Five I/O Two Output

Chopper Clock Yes

Package BGA

Part Number Le58083GC

BLOCK DESCRIPTIONS

Clock and Reference Circuits

This block generates a master clock and a frame sync signal for the digital circuits. It also generates an analog reference voltage for the analog circuits.

Microprocessor Interface MPI
• Removed standard non-green OPN from Ordering Information, on page 1
• Enhanced format of package drawing in Physical Dimensions, on page 93
• Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007

Zarlink Semiconductor Inc.

For more information about all Zarlink products visit our Web Site at

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries collectively “Zarlink” is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.

This publication is issued to provide information only and unless agreed by Zarlink in writing may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.

Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc.

TECHNICAL DOCUMENTATION - NOT FOR RESALE

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived LE58083ABGC Datasheet file may be downloaded here without warranties.

Datasheet ID: LE58083ABGC 648972