IDT5V9885CPFI8

IDT5V9885CPFI8 Datasheet

IDT5V9885C 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

Part	Datasheet
IDT5V9885CPFI8	IDT5V9885CPFI8 (pdf)

Related Parts	Information
IDT5V9885CNLGI	IDT5V9885CNLGI
IDT5V9885CNLGI8	IDT5V9885CNLGI8
IDT5V9885CPFGI	IDT5V9885CPFGI
IDT5V9885CPFGI8	IDT5V9885CPFGI8
IDT5V9885CPFI	IDT5V9885CPFI

PDF Datasheet Preview
IDT5V9885C 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE IDT5V9885C FEATURES: • Three internal PLLs • Internal non-volatile EEPROM • JTAG and FAST mode I2C serial interfaces • Input Frequency Ranges 1MHz to 400MHz • Output Frequency Ranges 4.9kHz to 500MHz • Reference Crystal Input with programmable oscillator gain and programmable linear load capacitance − Crystal Frequency Range 8MHz to 50MHz • Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider • 10-bit post-divider blocks • Fractional Dividers • Two of the PLLs support Spread Spectrum Generation capability • I/O Standards − Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS − Inputs - 3.3V LVTTL/ LVCMOS • Programmable Slew Rate Control • Programmable Loop Bandwidth Settings • Programmable output inversion to reduce bimodal jitter • Redundant clock inputs with glitchless auto and manual switchover options • JTAG Boundary Scan • Individual output enable/disable • Power-down mode • 3.3V VDD • Available in TQFP and VFQFPN packages DESCRIPTION: The IDT5V9885C is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. The IDT5V9885C can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in-system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented. Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs. There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function can be programmed. The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 c 2009 Integrated Device Technology, Inc. DECEMBER 2009 DSC 7117/4 IDT5V9885C 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR FUNCTIONAL BLOCK DIAGRAM XTALOUT XTALIN/REFIN OSC. CLKIN SHUTDOWN/OE GIN5/CLK_SEL I 2 C/JTAG PLL 0 PLL 1 PLL 2 EEPROM Control Block for Multi-Purpose I/O, Programming, Features INDUSTRIAL TEMPERATURE RANGE P2 Divider 10-Bit P3 Divider 10-Bit P4 Divider 10-Bit P5 Divider 10-Bit P6 Divider 10-Bit OUT1 OUT2 OUT3 OUT4 1 OUT4 OUT5 1 OUT5 1

PDF Datasheet Preview

IDT5V9885C 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

INDUSTRIAL TEMPERATURE RANGE

IDT5V9885C

FEATURES:
• Three internal PLLs
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges 1MHz to 400MHz
• Output Frequency Ranges 4.9kHz to 500MHz
• Reference Crystal Input with programmable oscillator gain and
programmable linear load capacitance − Crystal Frequency Range 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation capability
• I/O Standards − Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS − Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual switchover options
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TQFP and VFQFPN packages

DESCRIPTION:

The IDT5V9885C is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.

The IDT5V9885C can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in-system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.

Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.

There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function can be programmed.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE 1
c 2009 Integrated Device Technology, Inc.

DECEMBER 2009

DSC 7117/4

IDT5V9885C 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

FUNCTIONAL BLOCK DIAGRAM

XTALOUT XTALIN/REFIN

OSC.

CLKIN

SHUTDOWN/OE

GIN5/CLK_SEL I 2 C/JTAG

PLL 0 PLL 1 PLL 2

EEPROM

Control Block for Multi-Purpose I/O, Programming, Features

INDUSTRIAL TEMPERATURE RANGE

P2 Divider
10-Bit

P3 Divider
10-Bit

P4 Divider
10-Bit

P5 Divider
10-Bit

P6 Divider
10-Bit

OUT1 OUT2

OUT3 OUT4 1

OUT4 OUT5 1 OUT5 1

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT5V9885CPFI8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT5V9885CPFI8 637300