CORE1553BRT-EBR-AN

CORE1553BRT-EBR-AN Datasheet

Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal

Part	Datasheet
CORE1553BRT-EBR-AN	CORE1553BRT-EBR-AN (pdf)

Related Parts	Information
CORE1553BRT-EBR-AR	CORE1553BRT-EBR-AR

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Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal Advanced v1.1 Product Summary Intended Use • 1553 Enhanced Bit Rate Remote Terminal RT • DMA Backend Interface to External Memory • Direct Backend Interface to Devices • Space and Avionic Applications Key Features • Supports Enhanced Bit Rate 1553 • 10 Mbps Time-Multiplexed Serial Data Bus • Interfaces to External RAM or Directly to Backend Device • Synchronous or Asynchronous Backend Interface • Encoders and Decoders Operate off 100 MHz Clock • Protocol Control and Memory Interface Operates off 50 MHz Clock • Interfaces to Standard RS485 Transceivers • Programmable Mode Code and Sub-Address Legality for Illegal Command Support • Memory Address Mapping Allowing Emulation of Legacy Remote Terminals • Fail-Safe State Machines • Fully Synchronous Operation Supported Families • • • • RTAX-S Core Deliverables • Netlist Version Compiled RTL Simulation Model, Compliant with Actel Integrated Design Environment IDE Netlist Compatible with the Actel Designer Place-and-Route Tool with and without I/O Pads • RTL Version VHDL or Verilog Core Source Code Synthesis Scripts • Actel-Developed Testbench VHDL Development System • Complete 1553BRT-EBR Implementation, Implemented in an AX1000 Synthesis and Simulation Support • Synthesis Exemplar , Design FPGA Compiler • Simulation Vital-Compliant VHDL Simulators and OVI-Compliant Verilog Simulators Verification and Compliance • Meets Requirements of Draft SAE AS5682 Standard 2005-10 • Actel-Developed Simulation Testbench Implements a Subset of the RT Test Plan MIL-HDBK-1553A for Protocol Verification • Protocol Control Derived from Core1553BRT, which Is Certified to MIL-STD-1553B RT Validation Test Plan MIL-HDBK-1553, Appendix A Contents General Description 2 Core1553BRT-EBR Device Requirements 4 Core1553BRT-EBR Verification and Compliance 4 Core1553BRT-EBR Fail-Safe State Machines 4 Enhanced Bit Rate 1553 Bus Overview 4 I/O Signal Descriptions 6 1553BRT-EBR Operation 14 Command Legalization Interface 18 Bus Transceivers 18 Typical RT Systems 18 Specifications 20 Transceiver Loopback Delays 25 Ordering Information 25 List of Changes 25 Datasheet Categories 26 February 2006 Advanced v1.1 2006 Actel Corporation Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal Core1553BRT-EBR provides a complete, dual-redundant 1553 enhanced bit rate EBR remote terminal RT apart from the transceivers required to interface to the bus. A typical system implementation using the Core1553BRT-EBR is shown in Figure 1 and Figure 2 on page ADC Memory Glue Logic Backend Interface BUSAIN BUSAINENn BUSAOUTEN BUSAOUT BUSBIN BUSBINENn BUSBOUTEN BUSBOUT RS485 Transceivers Command Illegality Block Command Legality Block Core1553BRT-EBR Actel FPGA Figure 1 • Typical Core1553BRT-EBR System At a high level, Core1553BRT-EBR simply provides a set of memory mapped sub-addresses that "receive data written to" or "transmit data read from." The core can be configured to directly connect to synchronous or asynchronous memory devices. Alternately, the core can directly connect to the backend devices, removing the need for the memory buffers. If memory is used, the core requires 2,048 words of memory, which can be shared with the local CPU. The core supports all 1553EBR mode codes and allows the user to designate as illegal any mode code or any particular sub-address for both transmit and receive operations. The command legalization can be done within the core or in an external command legality block via the command legalization interface. Advanced v1.1 Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal The core consists of six main blocks 1553EBR encoders, 1553EBR decoders, backend interface, command decoder, RT controller blocks, and a command legalization block see Figure BusA BusB Encoder Decoder RT Protocol Controller Command Decoder Backend Interface Memory 2048x16 Command Legalization Core1553BRT-EBR Figure 2 • Core1553BRT-EBR RT Block Diagram In the Core1553BRT-EBR, a single 1553EBR encoder is used. This takes each word to be transmitted and serializes it, after which the signal is Manchester encoded. The encoder also includes both logic to prevent the RT from transmitting for greater than the allowed period and loopback fail logic. The loopback logic monitors the received data and verifies that the core has correctly received every word that it transmits. The output of the encoder is gated with the bus enable signals to select which buses the RT should use to transmit. The core includes two 1553EBR decoders. The decoder takes the serial Manchester data received from the bus and extracts the received data words. The decoder requires a 100 MHz clock to extract the data and the clock from the serial stream. The decoder contains a digital phased-lock loop PLL that generates a recovery clock used to sample the incoming serial data. The data is then deserialized and the 16-bit word decoded. The decoder detects whether a command or data word is received, and also performs Manchester encoding and parity error checking. The backend interface for the Core1553BRT-EBR allows a simple connection to a memory device or direct connection to other devices, such as analog-to-digital converters. The access rates to this memory are slow, with one read or write every 2 µs. The backend interface operates off the internally derived 50 MHz clock, resulting in a read or write every 100 clock cycles. The backend interface can be configured to connect to either synchronous or asynchronous memory devices. This Ordering Information Core1553BRT-EBR can be ordered through your local Actel sales representative. It should be ordered using the following number scheme Core1553BRT-EBR-XX, where XX is listed in Table Table 18 • Ordering Codes EV Evaluation version SN Netlist for single-use on Actel devices AN Netlist for unlimited use on Actel devices SR RTL for single-use on Actel devices AR RTL for unlimited use on Actel devices UR RTL for unlimited use and not restricted to Actel devices List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version A dv anced v 1 Advanced v1.0 The product name was changed from Core1553EBRRT to Core1553BRT-EBR. Changed "MIL-STD-1553EBR" to "MIL-STD-1553B" under "Verification and Compliance" First bullet added under "Verification and Compliance" Changed "SAE AIR5610" to "SAE AS5682" under "RT-to-RT Transfer Support" Changed Time values in Table 17 Changed maximum loopback delay under "Transceiver Loopback Delays" Page N/A 1 14 24 25 Advanced v1.1 Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definition of these categories are as follows: The product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked production This datasheet version contains information that is considered to be final. Advanced v1.1 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone Fax Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 0 1276 401 450 Fax +44 0 1276 401 490 Actel Japan EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone Fax Actel Hong Kong Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852 2185 6460 Fax +852 2185 6488

PDF Datasheet Preview

Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal

Advanced v1.1

Product Summary

Intended Use
• 1553 Enhanced Bit Rate Remote Terminal RT
• DMA Backend Interface to External Memory
• Direct Backend Interface to Devices
• Space and Avionic Applications

Key Features
• Supports Enhanced Bit Rate 1553
• 10 Mbps Time-Multiplexed Serial Data Bus
• Interfaces to External RAM or Directly to Backend

Device
• Synchronous or Asynchronous Backend Interface
• Encoders and Decoders Operate off 100 MHz Clock
• Protocol Control and Memory Interface Operates
off 50 MHz Clock
• Interfaces to Standard RS485 Transceivers
• Programmable Mode Code and Sub-Address

Legality for Illegal Command Support
• Memory Address Mapping Allowing Emulation of

Legacy Remote Terminals
• Fail-Safe State Machines
• Fully Synchronous Operation

Supported Families
•
•
•
• RTAX-S

Core Deliverables
• Netlist Version Compiled RTL Simulation Model, Compliant with Actel Integrated Design Environment IDE Netlist Compatible with the Actel Designer Place-and-Route Tool with and without I/O Pads
• RTL Version VHDL or Verilog Core Source Code Synthesis Scripts
• Actel-Developed Testbench VHDL

Development System
• Complete 1553BRT-EBR Implementation, Implemented in an AX1000

Synthesis and Simulation Support
• Synthesis Exemplar , Design FPGA Compiler
• Simulation Vital-Compliant VHDL Simulators and OVI-Compliant Verilog Simulators

Verification and Compliance
• Meets Requirements of Draft SAE AS5682 Standard 2005-10
• Actel-Developed Simulation Testbench Implements a Subset of the RT Test Plan MIL-HDBK-1553A for Protocol Verification
• Protocol Control Derived from Core1553BRT, which Is Certified to MIL-STD-1553B RT Validation Test Plan MIL-HDBK-1553, Appendix A

Contents
General Description 2 Core1553BRT-EBR Device Requirements 4 Core1553BRT-EBR Verification and Compliance 4 Core1553BRT-EBR Fail-Safe State Machines 4 Enhanced Bit Rate 1553 Bus Overview 4 I/O Signal Descriptions 6 1553BRT-EBR Operation 14 Command Legalization Interface 18 Bus Transceivers 18 Typical RT Systems 18 Specifications 20 Transceiver Loopback Delays 25 Ordering Information 25 List of Changes 25 Datasheet Categories 26

February 2006

Advanced v1.1
2006 Actel Corporation

Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal

Core1553BRT-EBR provides a complete, dual-redundant 1553 enhanced bit rate EBR remote terminal RT apart from the transceivers required to interface to the bus. A typical system implementation using the Core1553BRT-EBR is shown in Figure 1 and Figure 2 on page

ADC Memory

Glue Logic

Backend Interface

BUSAIN BUSAINENn BUSAOUTEN

BUSAOUT

BUSBIN BUSBINENn BUSBOUTEN

BUSBOUT

RS485 Transceivers

Command Illegality

Block Command Legality Block

Core1553BRT-EBR

Actel FPGA

Figure 1
• Typical Core1553BRT-EBR System

At a high level, Core1553BRT-EBR simply provides a set of memory mapped sub-addresses that "receive data written to" or "transmit data read from." The core can be configured to directly connect to synchronous or asynchronous memory devices. Alternately, the core can directly connect to the backend devices, removing the need for the memory buffers. If memory is used, the core
requires 2,048 words of memory, which can be shared with the local CPU.

The core supports all 1553EBR mode codes and allows the user to designate as illegal any mode code or any particular sub-address for both transmit and receive operations. The command legalization can be done within the core or in an external command legality block via the command legalization interface.

Advanced v1.1

Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal

The core consists of six main blocks 1553EBR encoders, 1553EBR decoders, backend interface, command decoder, RT controller blocks, and a command legalization block see Figure

BusA BusB

Encoder

Decoder

RT Protocol Controller

Command Decoder

Backend Interface

Memory 2048x16

Command Legalization

Core1553BRT-EBR

Figure 2
• Core1553BRT-EBR RT Block Diagram

In the Core1553BRT-EBR, a single 1553EBR encoder is used. This takes each word to be transmitted and serializes it, after which the signal is Manchester encoded. The encoder also includes both logic to prevent the RT from transmitting for greater than the allowed period and loopback fail logic. The loopback logic monitors the received data and verifies that the core has correctly received every word that it transmits.

The output of the encoder is gated with the bus enable signals to select which buses the RT should use to transmit.

The core includes two 1553EBR decoders. The decoder takes the serial Manchester data received from the bus and extracts the received data words. The decoder requires a 100 MHz clock to extract the data and the clock from the serial stream.

The decoder contains a digital phased-lock loop PLL that generates a recovery clock used to sample the incoming serial data. The data is then deserialized and the 16-bit word decoded. The decoder detects whether a command or data word is received, and also performs Manchester encoding and parity error checking.

The backend interface for the Core1553BRT-EBR allows a simple connection to a memory device or direct connection to other devices, such as analog-to-digital converters. The access rates to this memory are slow, with one read or write every 2 µs. The backend interface operates off the internally derived 50 MHz clock, resulting in a read or write every 100 clock cycles.

The backend interface can be configured to connect to either synchronous or asynchronous memory devices. This
Ordering Information

Core1553BRT-EBR can be ordered through your local Actel sales representative. It should be ordered using the following number scheme Core1553BRT-EBR-XX, where XX is listed in Table
Table 18
• Ordering Codes

EV Evaluation version

SN Netlist for single-use on Actel devices

AN Netlist for unlimited use on Actel devices

SR RTL for single-use on Actel devices

AR RTL for unlimited use on Actel devices

UR RTL for unlimited use and not restricted to Actel devices

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version

Changes in Current Version A dv anced v 1

Advanced v1.0

The product name was changed from Core1553EBRRT to Core1553BRT-EBR.

Changed "MIL-STD-1553EBR" to "MIL-STD-1553B" under "Verification and Compliance"

First bullet added under "Verification and Compliance"

Changed "SAE AIR5610" to "SAE AS5682" under "RT-to-RT Transfer Support"

Changed Time values in Table 17

Changed maximum loopback delay under "Transceiver Loopback Delays"

Page N/A
1 14 24 25

Advanced v1.1

Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal

Datasheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definition of these categories are as follows:

The product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products.

Advanced

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.

Unmarked production

This datasheet version contains information that is considered to be final.

Advanced v1.1

Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.

Actel Corporation
2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone Fax

Actel Europe Ltd.

Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 0 1276 401 450 Fax +44 0 1276 401 490

Actel Japan

EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan

Phone Fax

Actel Hong Kong

Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong

Phone +852 2185 6460 Fax +852 2185 6488

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CORE1553BRT-EBR-AN Datasheet file may be downloaded here without warranties.

Datasheet ID: CORE1553BRT-EBR-AN 648929