VSC8558XHJ

VSC8558XHJ Datasheet

VSC8558

Part	Datasheet
VSC8558XHJ	VSC8558XHJ (pdf)

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Downloaded by on June 1, 2009 from Vitesse.com VSC8558 Octal 10/100/1000BASE-T PHY with Dual Gbps SerDes Datasheet Downloaded by on June 1, 2009 from Vitesse.com Vitesse Corporate Headquarters 741 Calle Plano Camarillo, California 93012 United States Copyright by Vitesse Semiconductor Corporation Vitesse Semiconductor Corporation “Vitesse” retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Vitesse for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. Vitesse products are not intended for use in life support products where failure of a Vitesse product could reasonably be expected to result in death or personal injury. Anyone using a Vitesse product in such an application without express written consent of an officer of Vitesse does so at their own risk, and agrees to fully indemnify Vitesse for any damages that may result from such use or sale. Vitesse Semiconductor Corporation is a registered trademark. All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their respective holders. June 2006 Page 2 of 108 Downloaded by on June 1, 2009 from Vitesse.com VSC8558 Datasheet Contents Contents 1 Introduction 14 2 Product Overview 15 Features and Benefits 15 Block Diagram 17 3 Functional Descriptions 18 Operating 18 SerDes MAC-to-Cat5 Mode MAC 19 SGMII MAC-to-Cat5 Mode MAC Interface 20 All Modes Cat5 Media Interface 21 SerDes Media 21 SGMII MAC-to-100BASE-FX Mode 22 Automatic Media-Sense AMS Interface Mode 22 Cat5 Auto-Negotiation 24 Manual MDI/MDI-X Setting 24 Automatic Crossover and Polarity Detection 25 Link Speed Downshift 25 Transformer-less Ethernet 26 Ethernet In-line Powered Devices 26 802.3af PoE Support 28 ActiPHY Power Management 28 Low Power State 29 Link Partner Wake-up State 29 Normal Operating State 30 Serial Management Interface 30 SMI 30 SMI 31 LED Interface 32 LED Modes 33 LED 34 Serial LED 34 GPIO Pins 35 Testing Features 36 Ethernet Packet Generator EPG 36 CRC Counters 36 Far-end Loopback 37 Near-end Loopback 37 Connector Loopback 37 VeriPHY Cable Diagnostics 38 IEEE JTAG Boundary Scan 39 JTAG Instruction Codes 40 Boundary Scan Register Cell Order 41 IEEE AC-JTAG Boundary Scan Interface 41 June 2006 Page 3 of 108 Downloaded by on June 1, 2009 from Vitesse.com VSC8558 Datasheet Contents 4 Configuration 42 Registers 42 Reserved 43 Reserved Bits 43 IEEE Standard and Main Registers 44 Mode 45 Mode Status 46 Device 47 Auto-Negotiation 47 Link Partner Auto-Negotiation Capability 48 Auto-Negotiation 48 Transmit Auto-Negotiation Next Page 49 Auto-Negotiation Link Partner Next Page Receive........................... 49 1000BASE-T Control 50 1000BASE-T Status 50 Main Registers Reserved Addresses 51 1000BASE-T Status Extension 1 51 100BASE-TX Status 51 1000BASE-T Status Extension 2 52 Bypass Control 53 Reserved Address Space 53 Extended Control and Status 54 Extended PHY Control Set 55 Extended PHY Control Set 56 Interrupt 57 Interrupt 57 MAC Interface Auto-Negotiation Control and Status 58 Device Auxiliary Control and Status 59 LED Mode Select 60 LED 61 Extended Page Registers 62 Extended Page Access 63 SerDes Media Control 64 SerDes MAC Control 64 CRC Good Counter 65 SIGDET Control 65 Extended PHY Control 65 EEPROM Interface Status and Control 66 EEPROM Data 67 PoE and Miscellaneous 67 VeriPHY Control 68 VeriPHY Control 68 VeriPHY Control 68 Reserved Extended Registers 69 Ethernet Packet Generator Control 69 Ethernet Packet Generator Control 70 General-Purpose I/O Registers 71 Reserved GPIO 71 SIGDET Control Register 71 GPIO Input Register 72 GPIO Output Register 72 June 2006 Page 4 of 108 Downloaded by on June 1, 2009 from Vitesse.com VSC8558 Datasheet Contents GPIO Pin Configuration 72 100BASE-FX Control 73 CMODE Pins and Related 74 Functions and Related CMODE 74 CMODE Resistor Values 76 EEPROM 77 EEPROM Contents Description 77 Read/Write Access to the EEPROM 79 5 Electrical 81 DC 81 VDDIO at 81 VDDIO at 82 VDDIO at 82 VDD at V 83 MAC and SerDes Outputs 83 MAC and SerDes Inputs 84 LED Pins 84 JTAG 85 Current Consumption 85 AC Characteristics 86 Reference Clock 86 Clock Output 87 JTAG Interface 87 SMI Interface 88 Device Reset 89 Serial LEDs 90 Operating Conditions 91 Stress Ratings 91 6 Pin Descriptions 92 9 Ordering Information 108 Downloaded by on June 1, 2009 from Vitesse.com June 2006 Page 6 of 108 Downloaded by on June 1, 2009 from Vitesse.com VSC8558 Datasheet Contents Figures Figure Typical 15 Figure High-level Block Diagram 17 Figure SerDes MAC 20 Figure SGMII MAC Interface 20 Figure Cat5 Media Interface 21 Figure Automatic Media Sense Block 23 Figure In-line Powered Ethernet Switch Diagram 27 Figure ActiPHY State Diagram 29 Figure SMI Read Frame 30 Figure SMI Write 31 Figure MDINT_n Configured as an Open-Drain Active-low Pin 32 Figure MDINT_n Configured as an Open-source Active-high Pin 32 Figure Far-end Loopback Diagram 37 Figure Near-end Loopback 37 Figure Connector Loopback Diagram 38 Figure Test Access Port and Boundary Scan Architecture Diagram 39 Figure Register Space 43 Figure EEPROM Read and Write Register Flow 79 Figure JTAG Interface Timing 88 Figure SMI Interface Timing 89 Figure Reset Timing 90 Figure Serial LED Timing 90 Figure Pin Diagram, Left Side, Top 92 Figure Pin Diagram, Right Side, Top 93 Figure Package Drawing June 2006 Page 7 of 108 Downloaded by on June 1, 2009 from Vitesse.com VSC8558 Datasheet Contents Tables Table Features and Benefits 15 Operating Mode versus 18 AMS Media Preferences 23 Supported MDI Pair Combinations 25 LED Mode and Function Summary 33 LED Serial Stream Order 35 JTAG Device Identification Register Description 40 JTAG Interface Instruction Codes 40 IEEE Standard Registers 44 Main Registers 44 Mode Control, Address 0 45 Mode Status, Address 1 0x01 46 Identifier 1, Address 2 47 Identifier 2, Address 3 47 Device Auto-Negotiation Advertisement, Address 4 0x04 47 Auto-Negotiation Link Partner Ability, Address 5 0x05 ....................... 48 Auto-Negotiation Expansion, Address 6 48 Auto-Negotiation Next Page Transmit, Address 7 0x07 49 Auto-Negotiation LP Next Page Receive, Address 8 0x08 49 1000BASE-T Control, Address 9 0x09 50 1000BASE-T Status, Address 10 0x0A 50 1000BASE-T Status Extension 1, Address 15 0x0F 51 100BASE-TX Status Extension, Address 16 0x10 51 1000BASE-T Status Extension 2, Address 17 0x11 52 Bypass Control, Address 18 53 Extended Control and Status, Address 22 0x16 54 Extended PHY Control 1, Address 23 0x17 55 Extended PHY Control 2, Address 24 0x18 56 Interrupt Mask, Address 25 57 Interrupt Status, Address 26 0x1A 57 MAC Auto-Negotiation Control and Status, Address 27 0x1B .............. 58 Auxiliary Control and Status, Address 28 0x1C 59 LED Mode Select, Address 29 0x1D 60 Available LED Mode 61 LED Behavior, Address 30 0x1E 61 Extended Registers Page 63 Extended Page Access, Address 31 63 SerDes Media Auto-Negotiation Control/Status, Address 16E 0x10 64 SerDes MAC Control, Address 17E 64 CRC Good Counter, Address 18E 0x12 65 SIGDET Control, Address 19E 0x13 65 ActiPHY Control, Address 20E 0x14 65 EEPROM Interface Status and Control, Address 21E 0x15 .................. 66 EEPROM Read or Write, Address 22E 0x16 67 Extended PHY Control 4, Address 23E 67 VeriPHY Control Register 1, Address 24E 0x18 68 VeriPHY Control Register 2, Address 25E 0x19 68 VeriPHY Control Register 3, Address 26E 0x1A ................................. 69 June 2006 Page 8 of 108 Downloaded by on June 1, 2009 from Vitesse.com VSC8558 Datasheet Contents Table VeriPHY Control Register 3 Fault Codes 69 EPG Control Register 1, Address 29E 69 EPG Control Register 2, Address 30E 0x1E 70 General-Purpose Registers Page 71 SIGDET Control, Address 13G 0x0D 71 GPIO Input, Address 15G 0x0F 72 GPIO Output, Address 16G 72 GPIO Input/Output Configuration, Address 17G 0x11 72 100BASE-FX Control, Address 18G 0x12 73 CMODE Configuration Pins and Device Functions 74 Device Functions and Associated CMODE Pins 74 CMODE Resistor Values and Resultant Bit Settings 76 EEPROM Configuration 77 DC Characteristics for Pins Referenced to VDDIO at V 81 DC Characteristics for Pins Referenced to VDDIO at V 82 DC Characteristics for Pins Referenced to VDDIO at V 82 DC Characteristics for Pins Referenced to VDD33 at V 83 DC Characteristics for MAC_RDP/N_n and SER_DOP/N_n Pins 83 DC Characteristics for MAC_TDP/N_n and SER_DIP/N_n Pins 84 DC Characteristics for LED[3:0]_n Pins 84 DC Characteristics for JTAG 85 Typical Current Consumption 85 Current Consumption in SerDes/SGMII to 1000BASE-X Mode 86 AC Characteristics for REFCLK Input 86 AC Characteristics for REFCLK Input with 25 MHz Clock Input 87 AC Characteristics for the CLKOUT Pin 87 AC Characteristics for the JTAG 87 AC Characteristics for the SMI Interface 88 AC Characteristics for Device Reset 89 AC Characteristics for Serial 90 Recommended Operating 91 Stress Ratings 91 SerDes MAC Interface Pins 94 SerDes Media Interface Pins 95 GPIO and SIGDET 96 Twisted Pair Interface 96 SMI Pins 98 JTAG 98 Power Supply 99 Power Supply and Associated Function Pins Miscellaneous Pins Thermal Ordering June 2006 Page 9 of 108 Downloaded by on June 1, 2009 from Vitesse.com VSC8558 Datasheet • In the DC characteristics for VDDIO at V, the output leakage IOLEAK was changed to match the same values as the input leakage IILEAK with the same condition internal resistor included . Specifically, the values were changed from µA minimum and 10 µA maximum to µA minimum and 42 µA maximum. • In the DC characteristics for VDDIO at V, the output leakage IOLEAK was changed to match the same values as the input leakage IILEAK with the same condition internal resistor included . Specifically, the values were changed from µA minimum and 10 µA maximum to µA minimum and 32 µA maximum. • In the DC characteristics for VDDIO at V, the output leakage IOLEAK was changed to match the same values as the input leakage IILEAK with the same condition internal resistor included . Specifically, the values were changed from µA minimum and 10 µA maximum to µA minimum and 23 µA maximum. • In the DC characteristics for VDDIO at V, for the output high and low voltage parameters, new conditions were added to correlate with the output high and low current drive strength. The output high current drive strength parameter was updated from mA to mA maximum. The output low current drive strength parameter was updated from mA to mA. For more information, see Table 64, page • In the DC characteristics for VDD33 at V, the output leakage IOLEAK was changed to match the same values as the input leakage IILEAK with the same condition internal resistor included . Specifically, the values were changed from µA minimum and 10 µA maximum to µA minimum and 42 µA maximum. • For the MAC and SerDes DC output characteristics, the output differential voltage was updated from 350 mV minimum, 1200 mV typical, and 1400 mV maximum to 700 mV minimum, 1000 mV typical, and 1200 mV maximum. The output rise and fall time was updated from 300 ps maximum to 200 ps maximum, and the typical value 120 ps was added. Random and deterministic jitter specifications including footnotes were removed and replaced with the total jitter specification. The total receive jitter tolerance parameter was added. For more information about these characteristics, see Table 66, page • In the DC characteristics for LED pins, a qualifier in the introductory paragraph was removed stating that these specifications are valid only when a voltage range of V to V is applied to the LED pins. For the output high and low voltage parameters, new conditions were added to correlate with the output high and low current drive strength. The output high current drive strength parameter was updated from mA to mA maximum. The output low current drive strength parameter was updated from mA to mA minimum. For more information, see Table 68, page June 2006 Page 10 of 108 Downloaded by on June 1, 2009 from Vitesse.com VSC8558 Datasheet • In the DC characteristics for JTAG pins, the output leakage IOLEAK was changed to match the same values as the input leakage IILEAK with the same condition internal resistor included . Specifically, the values were changed from µA minimum and 10 µA maximum to µA minimum and 42 µA maximum. • For the current consumption specifications, the power consumption parameter was renamed from “worst case” to “full traffic conditions” to be technically accurate. The power consumption maximum was updated from TBD to W in typical consumption mode and, for the SerDes/SGMII to 1000BASE-X mode, the maximum was updated from TBD to W. Also, in the introductory text, a reference to 64-bit was corrected to 64-byte. For more information about current consumption, see Table 70, page 85 and Table 71, page • For the AC clock output characteristics, the total jitter values were changed from TBD to 217 ps typical and 491 ps maximum. • In the stress ratings, the power supply voltage parameter was removed because it was redundant. For the DC input voltage on the VDD12 and VDD12A supply pins, the maximum was updated from V to V. The electrostatic discharge voltage was specified as meeting a Class 2 rating. For more information about the Class 2 rating, see Table 80, page • For the serial management interface SMI pins, it was clarified that EECLK and EEDAT are referenced to VDD33, not VDDIO. Introduction and Overview • The VSC8558 device now supports the 100BASE-FX communication speed. • In the high-level block diagram, representation of the XTAL pin was corrected from “XTAL 1/2” to “XTAL1” and “XTAL2.” Omission of the “1000” speed was corrected. Functional Descriptions • The figures for the SerDes MAC interface and SGMII MAC interface were clarified to show that the TDP and TDN pins are capacitors in series within the VSC8558 device. • In the Cat5 Media Interface figure, the pinout order for the RJ45 was corrected. • The bandwidth provided by the SerDes block was previously stated to be full-duplex. It can also be half-duplex. • New information was added about how to manually force the device to use MDI/MDI-X. • For better document organization, the power-over-Ethernet PoE information now has its own heading. • In the far-end loopback diagram, the loopback arrow for the PHY port was redrawn closer to the MAC to more accurately portray the data path. June 2006 Page 11 of 108 VSC8558 Datasheet Downloaded by on June 1, 2009 from Vitesse.com • For the JTAG IDCODE binary values, the device version number was corrected from 0000 to The model number was corrected to be 8558 in binary . Configuration Registers • In the mode status register address 1 , the descriptions for bits 14:13 were corrected from 100BASE-X to 100BASE-TX. • In the identifier 2 register address 3 , which enables device identification, the default for bits 9:4 was modified from 0010000 to The default for bits 3:0 was modified from 0000 to • In the extended PHY control 1 register address 23 , missing bit information was added for the AMS preference parameter bit 11 , the media operating mode parameter bits 10:8 , and the force AMS override parameter bits • In the interrupt mask register address 25 , missing bit information was added for the AMS media changed mask parameter bit VSC8558 Datasheet Ordering Information Ordering Information Table The VSC8558 device is available in two package types. VSC8558HJ is a 444-pin, thermally enhanced, plastic ball grid array BGA with a 27 mm x 27 mm body size, 1 mm pin pitch, and mm maximum height. The device is also available in a lead Pb -free package, VSC8558XHJ. Lead Pb -free products from Vitesse comply with the temperatures and profiles defined in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard. The following table lists the ordering information for the VSC8558 device. Ordering Information Part Order Number VSC8558HJ VSC8558XHJ 444-pin, thermally enhanced, plastic ball grid array BGA with a 27 mm x 27 mm body size, 1 mm pin pitch, and mm maximum height Lead Pb -free, 444-pin, thermally enhanced, plastic ball grid array BGA with a 27 mm x 27 mm body size, 1 mm pin pitch, and mm maximum height June 2006 108 Page 108 of 108

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VSC8558

Octal 10/100/1000BASE-T PHY with Dual Gbps SerDes

Datasheet

Downloaded by on June 1, 2009 from Vitesse.com

Vitesse Corporate Headquarters 741 Calle Plano Camarillo, California 93012 United States

Copyright by Vitesse Semiconductor Corporation

Vitesse Semiconductor Corporation “Vitesse” retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Vitesse for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer.

Vitesse products are not intended for use in life support products where failure of a Vitesse product could reasonably be expected to result in death or personal injury. Anyone using a Vitesse product in such an application without express written consent of an officer of Vitesse does so at their own risk, and agrees to fully indemnify Vitesse for any damages that may result from such use or sale.

Vitesse Semiconductor Corporation is a registered trademark. All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their respective holders.

June 2006

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VSC8558 Datasheet Contents

Contents
1 Introduction 14
2 Product Overview 15

Features and Benefits 15 Block Diagram 17
3 Functional Descriptions 18

Operating 18 SerDes MAC-to-Cat5 Mode MAC 19 SGMII MAC-to-Cat5 Mode MAC Interface 20 All Modes Cat5 Media Interface 21

SerDes Media 21 SGMII MAC-to-100BASE-FX Mode 22 Automatic Media-Sense AMS Interface Mode 22 Cat5 Auto-Negotiation 24 Manual MDI/MDI-X Setting 24 Automatic Crossover and Polarity Detection 25 Link Speed Downshift 25 Transformer-less Ethernet 26 Ethernet In-line Powered Devices 26 802.3af PoE Support 28 ActiPHY Power Management 28

Low Power State 29 Link Partner Wake-up State 29 Normal Operating State 30 Serial Management Interface 30 SMI 30 SMI 31 LED Interface 32 LED Modes 33 LED 34 Serial LED 34 GPIO Pins 35 Testing Features 36 Ethernet Packet Generator EPG 36 CRC Counters 36 Far-end Loopback 37 Near-end Loopback 37 Connector Loopback 37 VeriPHY Cable Diagnostics 38 IEEE JTAG Boundary Scan 39 JTAG Instruction Codes 40 Boundary Scan Register Cell Order 41 IEEE AC-JTAG Boundary Scan Interface 41

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VSC8558 Datasheet Contents
4 Configuration 42

Registers 42 Reserved 43 Reserved Bits 43

IEEE Standard and Main Registers 44 Mode 45 Mode Status 46 Device 47 Auto-Negotiation 47 Link Partner Auto-Negotiation Capability 48 Auto-Negotiation 48 Transmit Auto-Negotiation Next Page 49 Auto-Negotiation Link Partner Next Page Receive........................... 49 1000BASE-T Control 50 1000BASE-T Status 50 Main Registers Reserved Addresses 51 1000BASE-T Status Extension 1 51 100BASE-TX Status 51 1000BASE-T Status Extension 2 52 Bypass Control 53 Reserved Address Space 53 Extended Control and Status 54 Extended PHY Control Set 55 Extended PHY Control Set 56 Interrupt 57 Interrupt 57 MAC Interface Auto-Negotiation Control and Status 58 Device Auxiliary Control and Status 59 LED Mode Select 60 LED 61

Extended Page Registers 62 Extended Page Access 63 SerDes Media Control 64 SerDes MAC Control 64 CRC Good Counter 65 SIGDET Control 65 Extended PHY Control 65 EEPROM Interface Status and Control 66 EEPROM Data 67 PoE and Miscellaneous 67 VeriPHY Control 68 VeriPHY Control 68 VeriPHY Control 68 Reserved Extended Registers 69 Ethernet Packet Generator Control 69 Ethernet Packet Generator Control 70

General-Purpose I/O Registers 71 Reserved GPIO 71 SIGDET Control Register 71 GPIO Input Register 72 GPIO Output Register 72

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VSC8558 Datasheet Contents

GPIO Pin Configuration 72 100BASE-FX Control 73 CMODE Pins and Related 74 Functions and Related CMODE 74 CMODE Resistor Values 76 EEPROM 77 EEPROM Contents Description 77 Read/Write Access to the EEPROM 79
5 Electrical 81

DC 81 VDDIO at 81 VDDIO at 82 VDDIO at 82 VDD at V 83 MAC and SerDes Outputs 83 MAC and SerDes Inputs 84 LED Pins 84 JTAG 85

Current Consumption 85 AC Characteristics 86

Reference Clock 86 Clock Output 87 JTAG Interface 87 SMI Interface 88 Device Reset 89 Serial LEDs 90 Operating Conditions 91 Stress Ratings 91
6 Pin Descriptions 92
9 Ordering Information 108

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VSC8558 Datasheet Contents

Figures

Figure Typical 15 Figure High-level Block Diagram 17 Figure SerDes MAC 20 Figure SGMII MAC Interface 20 Figure Cat5 Media Interface 21 Figure Automatic Media Sense Block 23 Figure In-line Powered Ethernet Switch Diagram 27 Figure ActiPHY State Diagram 29 Figure SMI Read Frame 30 Figure SMI Write 31 Figure MDINT_n Configured as an Open-Drain Active-low Pin 32 Figure MDINT_n Configured as an Open-source Active-high Pin 32 Figure Far-end Loopback Diagram 37 Figure Near-end Loopback 37 Figure Connector Loopback Diagram 38 Figure Test Access Port and Boundary Scan Architecture Diagram 39 Figure Register Space 43 Figure EEPROM Read and Write Register Flow 79 Figure JTAG Interface Timing 88 Figure SMI Interface Timing 89 Figure Reset Timing 90 Figure Serial LED Timing 90 Figure Pin Diagram, Left Side, Top 92 Figure Pin Diagram, Right Side, Top 93 Figure Package Drawing

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VSC8558 Datasheet Contents

Tables

Table

Features and Benefits 15 Operating Mode versus 18 AMS Media Preferences 23 Supported MDI Pair Combinations 25 LED Mode and Function Summary 33 LED Serial Stream Order 35 JTAG Device Identification Register Description 40 JTAG Interface Instruction Codes 40 IEEE Standard Registers 44 Main Registers 44 Mode Control, Address 0 45 Mode Status, Address 1 0x01 46 Identifier 1, Address 2 47 Identifier 2, Address 3 47 Device Auto-Negotiation Advertisement, Address 4 0x04 47 Auto-Negotiation Link Partner Ability, Address 5 0x05 ....................... 48 Auto-Negotiation Expansion, Address 6 48 Auto-Negotiation Next Page Transmit, Address 7 0x07 49 Auto-Negotiation LP Next Page Receive, Address 8 0x08 49 1000BASE-T Control, Address 9 0x09 50 1000BASE-T Status, Address 10 0x0A 50 1000BASE-T Status Extension 1, Address 15 0x0F 51 100BASE-TX Status Extension, Address 16 0x10 51 1000BASE-T Status Extension 2, Address 17 0x11 52 Bypass Control, Address 18 53 Extended Control and Status, Address 22 0x16 54 Extended PHY Control 1, Address 23 0x17 55 Extended PHY Control 2, Address 24 0x18 56 Interrupt Mask, Address 25 57 Interrupt Status, Address 26 0x1A 57 MAC Auto-Negotiation Control and Status, Address 27 0x1B .............. 58 Auxiliary Control and Status, Address 28 0x1C 59 LED Mode Select, Address 29 0x1D 60 Available LED Mode 61 LED Behavior, Address 30 0x1E 61 Extended Registers Page 63 Extended Page Access, Address 31 63 SerDes Media Auto-Negotiation Control/Status, Address 16E 0x10 64 SerDes MAC Control, Address 17E 64 CRC Good Counter, Address 18E 0x12 65 SIGDET Control, Address 19E 0x13 65 ActiPHY Control, Address 20E 0x14 65 EEPROM Interface Status and Control, Address 21E 0x15 .................. 66 EEPROM Read or Write, Address 22E 0x16 67 Extended PHY Control 4, Address 23E 67 VeriPHY Control Register 1, Address 24E 0x18 68 VeriPHY Control Register 2, Address 25E 0x19 68 VeriPHY Control Register 3, Address 26E 0x1A ................................. 69

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VSC8558 Datasheet Contents

Table
VeriPHY Control Register 3 Fault Codes 69 EPG Control Register 1, Address 29E 69 EPG Control Register 2, Address 30E 0x1E 70 General-Purpose Registers Page 71 SIGDET Control, Address 13G 0x0D 71 GPIO Input, Address 15G 0x0F 72 GPIO Output, Address 16G 72 GPIO Input/Output Configuration, Address 17G 0x11 72 100BASE-FX Control, Address 18G 0x12 73 CMODE Configuration Pins and Device Functions 74 Device Functions and Associated CMODE Pins 74 CMODE Resistor Values and Resultant Bit Settings 76 EEPROM Configuration 77 DC Characteristics for Pins Referenced to VDDIO at V 81 DC Characteristics for Pins Referenced to VDDIO at V 82 DC Characteristics for Pins Referenced to VDDIO at V 82 DC Characteristics for Pins Referenced to VDD33 at V 83 DC Characteristics for MAC_RDP/N_n and SER_DOP/N_n Pins 83 DC Characteristics for MAC_TDP/N_n and SER_DIP/N_n Pins 84 DC Characteristics for LED[3:0]_n Pins 84 DC Characteristics for JTAG 85 Typical Current Consumption 85 Current Consumption in SerDes/SGMII to 1000BASE-X Mode 86 AC Characteristics for REFCLK Input 86 AC Characteristics for REFCLK Input with 25 MHz Clock Input 87 AC Characteristics for the CLKOUT Pin 87 AC Characteristics for the JTAG 87 AC Characteristics for the SMI Interface 88 AC Characteristics for Device Reset 89 AC Characteristics for Serial 90 Recommended Operating 91 Stress Ratings 91 SerDes MAC Interface Pins 94 SerDes Media Interface Pins 95 GPIO and SIGDET 96 Twisted Pair Interface 96 SMI Pins 98 JTAG 98 Power Supply 99 Power Supply and Associated Function Pins Miscellaneous Pins Thermal Ordering

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VSC8558 Datasheet
• In the DC characteristics for VDDIO at V, the output leakage IOLEAK was changed to match the same values as the input leakage IILEAK with the same condition internal resistor included . Specifically, the values were changed from µA minimum and 10 µA maximum to µA minimum and 42 µA maximum.
• In the DC characteristics for VDDIO at V, the output leakage IOLEAK was changed to match the same values as the input leakage IILEAK with the same condition internal resistor included . Specifically, the values were changed from µA minimum and 10 µA maximum to µA minimum and 32 µA maximum.
• In the DC characteristics for VDDIO at V, the output leakage IOLEAK was changed to match the same values as the input leakage IILEAK with the same condition internal resistor included . Specifically, the values were changed from µA minimum and 10 µA maximum to µA minimum and 23 µA maximum.
• In the DC characteristics for VDDIO at V, for the output high and low voltage parameters, new conditions were added to correlate with the output high and low current drive strength. The output high current drive strength parameter was updated from mA to mA maximum. The output low current drive strength parameter was updated from mA to mA. For more information, see Table 64, page
• In the DC characteristics for VDD33 at V, the output leakage IOLEAK was changed to match the same values as the input leakage IILEAK with the same condition internal resistor included . Specifically, the values were changed from µA minimum and 10 µA maximum to µA minimum and 42 µA maximum.
• For the MAC and SerDes DC output characteristics, the output differential voltage was updated from 350 mV minimum, 1200 mV typical, and 1400 mV maximum to 700 mV minimum, 1000 mV typical, and 1200 mV maximum. The output rise and fall time was updated from 300 ps maximum to 200 ps maximum, and the typical value 120 ps was added. Random and deterministic jitter specifications including footnotes were removed and replaced with the total jitter specification. The total receive jitter tolerance parameter was added. For more information about these characteristics, see Table 66, page
• In the DC characteristics for LED pins, a qualifier in the introductory paragraph was removed stating that these specifications are valid only when a voltage range of V to V is applied to the LED pins. For the output high and low voltage parameters, new conditions were added to correlate with the output high and low current drive strength. The output high current drive strength parameter was updated from mA to mA maximum. The output low current drive strength parameter was updated from mA to mA minimum. For more information, see Table 68, page

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VSC8558 Datasheet
• In the DC characteristics for JTAG pins, the output leakage IOLEAK was changed to match the same values as the input leakage IILEAK with the same condition internal resistor included . Specifically, the values were changed from µA minimum and 10 µA maximum to µA minimum and 42 µA maximum.
• For the current consumption specifications, the power consumption parameter was renamed from “worst case” to “full traffic conditions” to be technically accurate. The power consumption maximum was updated from TBD to W in typical consumption mode and, for the SerDes/SGMII to 1000BASE-X mode, the maximum was updated from TBD to W. Also, in the introductory text, a reference to 64-bit was corrected to 64-byte. For more information about current consumption, see Table 70, page 85 and Table 71, page
• For the AC clock output characteristics, the total jitter values were changed from TBD to 217 ps typical and 491 ps maximum.
• In the stress ratings, the power supply voltage parameter was removed because it was redundant. For the DC input voltage on the VDD12 and VDD12A supply pins, the maximum was updated from V to V. The electrostatic discharge voltage was specified as meeting a Class 2 rating. For more information about the Class 2 rating, see Table 80, page
• For the serial management interface SMI pins, it was clarified that EECLK and EEDAT are referenced to VDD33, not VDDIO.

Introduction and Overview
• The VSC8558 device now supports the 100BASE-FX communication speed.
• In the high-level block diagram, representation of the XTAL pin was corrected from “XTAL 1/2” to “XTAL1” and “XTAL2.” Omission of the “1000” speed was corrected.

Functional Descriptions
• The figures for the SerDes MAC interface and SGMII MAC interface were clarified to show that the TDP and TDN pins are capacitors in series within the VSC8558 device.
• In the Cat5 Media Interface figure, the pinout order for the RJ45 was corrected.
• The bandwidth provided by the SerDes block was previously stated to be full-duplex. It can also be half-duplex.
• New information was added about how to manually force the device to use MDI/MDI-X.
• For better document organization, the power-over-Ethernet PoE information now has its own heading.
• In the far-end loopback diagram, the loopback arrow for the PHY port was redrawn closer to the MAC to more accurately portray the data path.

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VSC8558 Datasheet

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• For the JTAG IDCODE binary values, the device version number was corrected from 0000 to The model number was corrected to be 8558 in binary .

Configuration Registers
• In the mode status register address 1 , the descriptions for bits 14:13 were corrected from 100BASE-X to 100BASE-TX.
• In the identifier 2 register address 3 , which enables device identification, the default for bits 9:4 was modified from 0010000 to The default for bits 3:0 was modified from 0000 to
• In the extended PHY control 1 register address 23 , missing bit information was added for the AMS preference parameter bit 11 , the media operating mode parameter bits 10:8 , and the force AMS override parameter bits
• In the interrupt mask register address 25 , missing bit information was added for the AMS media changed mask parameter bit
VSC8558 Datasheet Ordering Information
Ordering Information

Table

The VSC8558 device is available in two package types. VSC8558HJ is a 444-pin, thermally enhanced, plastic ball grid array BGA with a 27 mm x 27 mm body size, 1 mm pin pitch, and mm maximum height. The device is also available in a lead Pb -free package, VSC8558XHJ.

Lead Pb -free products from Vitesse comply with the temperatures and profiles defined in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
The following table lists the ordering information for the VSC8558 device.
Ordering Information

Part Order Number VSC8558HJ

VSC8558XHJ
444-pin, thermally enhanced, plastic ball grid array BGA with a 27 mm x 27 mm body size, 1 mm pin pitch, and mm maximum height

Lead Pb -free, 444-pin, thermally enhanced, plastic ball grid array BGA with a 27 mm x 27 mm body size, 1 mm pin pitch, and mm maximum height

June 2006
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Datasheet ID: VSC8558XHJ 649203