NAND04GR3B2DN6E

NAND04GR3B2DN6E Datasheet

NAND04G-B2D NAND08G-BxC

Part	Datasheet
NAND04GR3B2DN6E	NAND04GR3B2DN6E (pdf)

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NAND04G-B2D NAND08G-BxC 4-Gbit, 8-Gbit, 2112-byte/1056-word page multiplane architecture, V or 3 V, SLC NAND flash memories • High density NAND flash memory Up to 8 Gbits of memory array Cost-effective solution for mass storage applications • NAND interface x8 or x16 bus width Multiplexed address/data • Supply voltage V or 3 V device • Page size x8 device 2048 + 64 spare bytes x16 device 1024 + 32 spare words • Block size x8 device 128K + 4 K spare bytes x16 device 64K + 2K spare words • Multiplane architecture Array split into two independent planes Program/erase operations can be performed on both planes at the same time • Page read/program Random access 25 µs max Sequential access 25 ns min Page program time 200 µs typ Multiplane page program time 2 pages 200 µs typ • Copy back program with automatic error detection code EDC • Cache read mode • Fast block erase Block erase time ms typ Multiblock erase time 2 blocks ms typ • Status register • Electronic signature • Chip enable ‘don’t care’ • ONFI compliant command set TSOP48 12 x 20 mm N ULGA52 12 x 17 x mm ZL • Security features OTP area Serial number unique ID Non-volatile protection option • Data protection hardware program/erase disabled during power transitions • Data integrity 100,000 program/erase cycles with ECC 10 years data retention • RoHS compliant packages Table Device summary Reference NAND04G-B2D NAND08G-BxC NAND04GR3B2D NAND04GW3B2D NAND04GR4B2D 1 NAND04GW4B2D 1 NAND08GR3B2C, NAND08GW3B2C NAND08GR4B2C 1 NAND08GW4B2C 1 NAND08GR3B4C NAND08GW3B4C x16 organization only available for MCP products. February 2010 1/72 Contents Contents NAND04G-B2D, NAND08G-BxC Description 7 Memory array organization 14 Signals description 16 Inputs/outputs I/O0-I/O7 16 Inputs/outputs I/O8-I/O15 16 Address latch enable AL 16 Command latch enable CL 16 Chip enable E 16 Read enable R 16 Write enable W 17 Ordering information 69 4/72 NAND04G-B2D, NAND08G-BxC List of tables List of tables Table 5/72 List of figures List of figures NAND04G-B2D, NAND08G-BxC Figure Logic block diagram 9 Logic diagram 9 TSOP48 connections for NAND04G-B2D and NAND08G-BxC 11 ULGA52 connections for NAND04G-B2D and NAND08G-B2C devices 12 ULGA52 connections for the NAND08G-B4C devices 13 Memory array organization 15 Read operations 23 Random data output during sequential data output 24 Cache read sequential operation 25 Cache read random operation 25 Page program operation 27 Random data input during sequential data input 27 Multiplane page program waveform 29 Copy back program without readout of data 30 Copy back program with readout of data 31 Page copy back program with random data input 31 Multiplane copy back program 32 Block erase 33 Multiplane block erase 34 Page organization 35 Bad block management flowchart. 47 Garbage collection 48 Equivalent testing circuit for AC characteristics measurement 52 Command latch AC waveforms 55 Address latch AC waveforms 55 Data input latch AC waveforms 56 Sequential data output after read AC waveforms 56 Sequential data output after read AC waveforms EDO mode 57 Read status register or read EDC status register AC waveform. 57 Read status enhanced waveform 58 Read electronic signature AC waveform 58 Read ONFI signature waveform 59 Page read operation AC waveform. 60 Page program AC waveform 61 Block erase AC waveform 62 Reset AC waveform 62 Program/erase enable waveform 63 Program/erase disable waveform 63 Read parameter page waveform 64 Ready/busy AC waveform 65 Ready/busy load circuit. 65 Resistor value versus waveform timings for ready/busy signal 66 Data protection 66 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline 67 ULGA52 12 x 17 x mm, 1 mm pitch, package outline. 68 6/72 NAND04G-B2D, NAND08G-BxC The NAND04G-B2D and NAND08G-BxC are part of the NAND flash 2112-byte/1056-word page family of non-volatile flash memories. They use NAND cell technology have a density of 4 Gbits and 8 Gbits, respectively. The NAND04G-B2D memory array is split into 2 planes of 2048 blocks each. This multiplane architecture makes it possible to program 2 pages at a time one in each plane , or to erase 2 blocks at a time one in each plane . This feature reduces the average program and erase times by The NAND08G-BxC is a stacked device that combines two NAND04G-B2D dice, both of which feature a multiplane architecture. In the NAND08G-B2C devices, only one of the memory components can be enabled at a time, therefore, operations can only be performed on one of the memory components at any one time. The devices operate from a V or 3 V voltage supply. Depending on whether the device has a x8 or x16 bus width, the page size is 2112 bytes 2048 + 64 spare or 1056 words 1024 + 32 spare , respectively. The address lines are multiplexed with the data input/output signals on a multiplexed x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased up to 100,000 cycles with ECC error correction code on. To extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory. A write protect pin is available to provide hardware protection against program and erase operations. The devices feature an open-drain ready/busy output that identifies if the P/E/R program/erase/read controller is currently active. The use of an open-drain output allows the ready/busy pins from several memories to connect to a single pull-up resistor. A Copy Back Program command is available to optimize the management of defective blocks. When a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed. An embedded error detection code EDC is automatically executed after each copy back operation 1 error bit can be detected for every 528 bytes. With this feature it is no longer necessary to use an external ECC to detect copy back operation errors. The devices have a cache read feature that improves the read throughput for large files. During cache reading, the device loads the data in a cache register while the previous data is transferred to the I/O buffers to be read. The devices have the chip enable ‘don’t care’ feature, which allows code to be directly downloaded by a microcontroller. This is possible because chip enable transitions during the latency time do not stop the read operation. Both the NAND04G-B2D and NAND08G-BxC support the ONFI specification. The devices are available in the following packages ● TSOP48 12 x 20 mm ● ULGA52 12 x 17 x mm 7/72 NAND04G-B2D, NAND08G-BxC and come with three security features ● OTP one time programmable area, which is a restricted access area where sensitive data/code can be stored permanently ● Serial number unique identifier , which allows the device to be uniquely identified ● Non-volatile protection to lock sensible data permanently. These security features are subject to an NDA non-disclosure agreement and are, therefore, not described in the datasheet. For more details about them, contact your nearest Numonyx sales office. For information on how to order these options, refer to Table 34 Ordering information scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to Table 2 Product description lists the part numbers and other information for all the devices available in the family. Table Product description Density Bus width Page size Block size Timings Memory array Operating voltage Sequential access time min Random access time max Page Program Block Erase typ Package NAND04GR3B2D NAND04GW3B2D NAND04GR4B2D 4-Gbit NAND04GW4B2D NAND08GR3B2C NAND08GW3B2C NAND08GR4B2C NAND08GW4B2C 8-Gbit NAND08GR3B4C NAND08GW3B4C 2048+64 128K+ bytes 4K bytes 64 pages x 4096 blocks 1024+ 32 64K + words 2K words 2048+64 128K + bytes 4K bytes 1024+ 32 words 64K + 2K words 64 pages x 8192 blocks x8 2048+64 128K + bytes 4K bytes x8 45 ns 25 ns 45 ns 25 ns 45 ns 25 ns 45 ns 25 ns 45 ns 25 ns 25 µs ULGA52 200 µs TSOP48 ULGA52 ULGA52 2 TSOP48 ULGA52 2 14 Ordering information Ordering information Note: Table Ordering information scheme Example: NAND04GW3B2D N 6 E Device type NAND flash memory Density 04G = 4 Gbits 08G = 8 Gbits Operating voltage W = VDD = to V R = VDD = to V Bus width 3 = x8 4 = x16 1 Family identifier B = 2112-byte page Device options 2 = Chip Enable ‘don't care’ enabled 4 = Chip Enable ‘don’t care’ enabled with dual interface Product version C= third version NAND08G-BxC D = fourth version NAND04G-B2D Package N = TSOP48 12 x 20 mm ZL = ULGA52 12 x 17 x mm Temperature range 1 = 0 to 70 °C 6 = to 85 °C Option E = RoHS compliant package, standard packing F = RoHS compliant package, tape and reel packing x16 organization only available for MCP products Not all combinations are necessarily available. For a list of available devices of for further information on any aspect of these products, please contact your nearest Numonyx sales office. 69/72 NAND04G-B2D, NAND08G-BxC Changes 22-June-2007 Initial release. 17-Sep-2007 10-Dec-2007 Added the part numbers NAND08GR3B4C, NAND08GW3B4C, therefore referring to the 8-Gbit devices as the NAND08G-BxC. Modified all data throughout this document to reflect the addition of these part numbers, namely: Table 1, Table 2, Table 6, and Table Added Figure 5 ULGA52 connections for the NAND08G-B4C devices. Changed VLKO value in Table 28 from to Applied Numonyx branding. 23-Apr-2008 Modified Figure 6 Memory array organization, Figure 13: Multiplane page program waveform, Figure 17 Multiplane copy back program, Figure 19 Multiplane block erase, Figure 30: Read status enhanced waveform, Figure 37 Program/erase enable waveform, Figure 38 Program/erase disable waveform, and Figure 42 Resistor value versus waveform timings for ready/busy signal, Section Cache read, Section Multiplane page program, Section Copy back program, Section Multiplane block erase and Section Read ONFI signature, Table 24 Program erase times and program erase endurance cycles and Table 26 Operating and AC measurement conditions. Added ECOPACK text in Section 13 Package mechanical.

PDF Datasheet Preview

NAND04G-B2D NAND08G-BxC
4-Gbit, 8-Gbit, 2112-byte/1056-word page multiplane architecture, V or 3 V, SLC NAND flash memories
• High density NAND flash memory Up to 8 Gbits of memory array Cost-effective solution for mass storage applications
• NAND interface x8 or x16 bus width Multiplexed address/data
• Supply voltage V or 3 V device
• Page size x8 device 2048 + 64 spare bytes x16 device 1024 + 32 spare words
• Block size x8 device 128K + 4 K spare bytes x16 device 64K + 2K spare words
• Multiplane architecture Array split into two independent planes Program/erase operations can be performed on both planes at the same time
• Page read/program Random access 25 µs max Sequential access 25 ns min Page program time 200 µs typ Multiplane page program time 2 pages 200 µs typ
• Copy back program with automatic error detection code EDC
• Cache read mode
• Fast block erase Block erase time ms typ Multiblock erase time 2 blocks ms typ
• Status register
• Electronic signature
• Chip enable ‘don’t care’
• ONFI compliant command set

TSOP48 12 x 20 mm N

ULGA52 12 x 17 x mm ZL
• Security features OTP area Serial number unique ID Non-volatile protection option
• Data protection hardware program/erase disabled during power transitions
• Data integrity 100,000 program/erase cycles with ECC 10 years data retention
• RoHS compliant packages

Table Device summary

Reference

NAND04G-B2D NAND08G-BxC

NAND04GR3B2D NAND04GW3B2D NAND04GR4B2D 1 NAND04GW4B2D 1 NAND08GR3B2C, NAND08GW3B2C NAND08GR4B2C 1 NAND08GW4B2C 1 NAND08GR3B4C NAND08GW3B4C
x16 organization only available for MCP products.

February 2010
1/72

Contents

Contents

NAND04G-B2D, NAND08G-BxC

Description 7

Memory array organization 14

Signals description 16

Inputs/outputs I/O0-I/O7 16

Inputs/outputs I/O8-I/O15 16

Address latch enable AL 16

Command latch enable CL 16

Chip enable E 16

Read enable R 16

Write enable W 17
Ordering information 69
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NAND04G-B2D, NAND08G-BxC

List of tables

List of tables

Table
5/72

List of figures

List of figures

NAND04G-B2D, NAND08G-BxC

Figure

Logic block diagram 9 Logic diagram 9 TSOP48 connections for NAND04G-B2D and NAND08G-BxC 11 ULGA52 connections for NAND04G-B2D and NAND08G-B2C devices 12 ULGA52 connections for the NAND08G-B4C devices 13 Memory array organization 15 Read operations 23 Random data output during sequential data output 24 Cache read sequential operation 25 Cache read random operation 25 Page program operation 27 Random data input during sequential data input 27 Multiplane page program waveform 29 Copy back program without readout of data 30 Copy back program with readout of data 31 Page copy back program with random data input 31 Multiplane copy back program 32 Block erase 33 Multiplane block erase 34 Page organization 35 Bad block management flowchart. 47 Garbage collection 48 Equivalent testing circuit for AC characteristics measurement 52 Command latch AC waveforms 55 Address latch AC waveforms 55 Data input latch AC waveforms 56 Sequential data output after read AC waveforms 56 Sequential data output after read AC waveforms EDO mode 57 Read status register or read EDC status register AC waveform. 57 Read status enhanced waveform 58 Read electronic signature AC waveform 58 Read ONFI signature waveform 59 Page read operation AC waveform. 60 Page program AC waveform 61 Block erase AC waveform 62 Reset AC waveform 62 Program/erase enable waveform 63 Program/erase disable waveform 63 Read parameter page waveform 64 Ready/busy AC waveform 65 Ready/busy load circuit. 65 Resistor value versus waveform timings for ready/busy signal 66 Data protection 66 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline 67 ULGA52 12 x 17 x mm, 1 mm pitch, package outline. 68
6/72

NAND04G-B2D, NAND08G-BxC

The NAND04G-B2D and NAND08G-BxC are part of the NAND flash 2112-byte/1056-word page family of non-volatile flash memories. They use NAND cell technology have a density of 4 Gbits and 8 Gbits, respectively.

The NAND04G-B2D memory array is split into 2 planes of 2048 blocks each. This multiplane architecture makes it possible to program 2 pages at a time one in each plane , or to erase 2 blocks at a time one in each plane . This feature reduces the average program and erase times by

The NAND08G-BxC is a stacked device that combines two NAND04G-B2D dice, both of which feature a multiplane architecture.

In the NAND08G-B2C devices, only one of the memory components can be enabled at a time, therefore, operations can only be performed on one of the memory components at any one time.

The devices operate from a V or 3 V voltage supply. Depending on whether the device has a x8 or x16 bus width, the page size is 2112 bytes 2048 + 64 spare or 1056 words 1024 + 32 spare , respectively.

The address lines are multiplexed with the data input/output signals on a multiplexed x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.

Each block can be programmed and erased up to 100,000 cycles with ECC error correction code on. To extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory.

A write protect pin is available to provide hardware protection against program and erase operations.

The devices feature an open-drain ready/busy output that identifies if the P/E/R program/erase/read controller is currently active. The use of an open-drain output allows the ready/busy pins from several memories to connect to a single pull-up resistor.

A Copy Back Program command is available to optimize the management of defective blocks. When a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed. An embedded error detection code EDC is automatically executed after each copy back operation 1 error bit can be detected for every 528 bytes. With this feature it is no longer necessary to use an external ECC to detect copy back operation errors.

The devices have a cache read feature that improves the read throughput for large files. During cache reading, the device loads the data in a cache register while the previous data is transferred to the I/O buffers to be read.

The devices have the chip enable ‘don’t care’ feature, which allows code to be directly downloaded by a microcontroller. This is possible because chip enable transitions during the latency time do not stop the read operation.

Both the NAND04G-B2D and NAND08G-BxC support the ONFI specification.

The devices are available in the following packages ● TSOP48 12 x 20 mm ● ULGA52 12 x 17 x mm
7/72

NAND04G-B2D, NAND08G-BxC
and come with three security features ● OTP one time programmable area, which is a restricted access area where sensitive
data/code can be stored permanently ● Serial number unique identifier , which allows the device to be uniquely identified ● Non-volatile protection to lock sensible data permanently.

These security features are subject to an NDA non-disclosure agreement and are, therefore, not described in the datasheet. For more details about them, contact your nearest Numonyx sales office.
For information on how to order these options, refer to Table 34 Ordering information scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to

Table 2 Product description lists the part numbers and other information for all the devices available in the family.

Table Product description

Density

Bus width

Page size

Block size

Timings

Memory array

Operating voltage

Sequential access
time min

Random access time max

Page Program

Block Erase typ

Package

NAND04GR3B2D

NAND04GW3B2D NAND04GR4B2D
4-Gbit

NAND04GW4B2D

NAND08GR3B2C

NAND08GW3B2C

NAND08GR4B2C NAND08GW4B2C
8-Gbit

NAND08GR3B4C

NAND08GW3B4C
2048+64 128K+ bytes 4K bytes
64 pages x 4096 blocks
1024+ 32 64K + words 2K words
2048+64 128K + bytes 4K bytes
1024+ 32 words
64K + 2K words
64 pages x 8192 blocks
x8 2048+64 128K +
bytes 4K bytes x8
45 ns 25 ns 45 ns 25 ns 45 ns 25 ns 45 ns 25 ns 45 ns 25 ns
25 µs

ULGA52
200 µs

TSOP48 ULGA52

ULGA52 2 TSOP48 ULGA52 2
14 Ordering information
Ordering information

Note:
Table Ordering information scheme Example:

NAND04GW3B2D N 6 E

Device type NAND flash memory

Density 04G = 4 Gbits 08G = 8 Gbits

Operating voltage W = VDD = to V R = VDD = to V

Bus width 3 = x8 4 = x16 1

Family identifier B = 2112-byte page

Device options 2 = Chip Enable ‘don't care’ enabled 4 = Chip Enable ‘don’t care’ enabled with dual interface

Product version C= third version NAND08G-BxC D = fourth version NAND04G-B2D

Package N = TSOP48 12 x 20 mm ZL = ULGA52 12 x 17 x mm

Temperature range 1 = 0 to 70 °C 6 = to 85 °C

Option E = RoHS compliant package, standard packing F = RoHS compliant package, tape and reel packing
x16 organization only available for MCP products

Not all combinations are necessarily available. For a list of available devices of for further information on any aspect of these products, please contact your nearest Numonyx sales office.
69/72

NAND04G-B2D, NAND08G-BxC

Changes
22-June-2007

Initial release.
17-Sep-2007 10-Dec-2007

Added the part numbers NAND08GR3B4C, NAND08GW3B4C,
therefore referring to the 8-Gbit devices as the NAND08G-BxC.

Modified all data throughout this document to reflect the addition
of these part numbers, namely:

Table 1, Table 2, Table 6, and Table

Added Figure 5 ULGA52 connections for the NAND08G-B4C devices.

Changed VLKO value in Table 28 from to

Applied Numonyx branding.
23-Apr-2008

Modified Figure 6 Memory array organization, Figure 13:

Multiplane page program waveform, Figure 17 Multiplane copy
back program, Figure 19 Multiplane block erase, Figure 30:

Read status enhanced waveform, Figure 37 Program/erase
enable waveform, Figure 38 Program/erase disable waveform,
and Figure 42 Resistor value versus waveform timings for
ready/busy signal, Section Cache read, Section

Multiplane page program, Section Copy back program, Section Multiplane block erase and Section Read

ONFI signature, Table 24 Program erase times and program
erase endurance cycles and Table 26 Operating and AC
measurement conditions.

Added ECOPACK text in Section 13 Package mechanical.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived NAND04GR3B2DN6E Datasheet file may be downloaded here without warranties.

Datasheet ID: NAND04GR3B2DN6E 648539