MT9VDDT6472AY-335F1

MT9VDDT6472AY-335F1 Datasheet

MT9VDDT1672A 128MB MT9VDDT3272A 256MB MT9VDDT6472A 512MB

Part	Datasheet
MT9VDDT6472AY-335F1	MT9VDDT6472AY-335F1 (pdf)

Related Parts	Information
MT9VDDT6472AG-335D1	MT9VDDT6472AG-335D1
MT9VDDT3272AG-335G4	MT9VDDT3272AG-335G4
MT9VDDT6472AG-335F1	MT9VDDT6472AG-335F1
MT9VDDT3272AY-335G4	MT9VDDT3272AY-335G4
MT9VDDT3272AG-262G4	MT9VDDT3272AG-262G4
MT9VDDT3272AG-26AG4	MT9VDDT3272AG-26AG4
MT9VDDT3272AG-265G4	MT9VDDT3272AG-265G4

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128MB, 256MB, 512MB x72, ECC, SR , PC3200 184-Pin DDR SDRAM UDIMM DDR SDRAM UNBUFFERED DIMM MT9VDDT1672A 128MB MT9VDDT3272A 256MB MT9VDDT6472A 512MB For the latest data sheet, please refer to the Web site: • JEDEC-standard 184-pin dual in-line memory module DIMM • Fast data transfer rate PC3200 • CAS Latency 3 • Utilizes 400 MT/s DDR SDRAM components • Supports ECC error detection and correction • 128MB 16 Meg x 72 , 256MB 32 Meg x 72 , 512MB 64 Meg x 72 • VDD= VDDQ= +2.6V • VDDSPD = +2.3V to +3.6V • +2.6V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/ received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh Modes • 15.6µs 128MB , 7.8125µs 256MB, 512MB maximum average periodic refresh interval • Serial Presence-Detect SPD with EEPROM • Programmable READ CAS latency • Gold edge contacts Figure 1 184-Pin DIMM MO-206 Standard 1.25in. 31.75mm OPTIONS • Package 184-pin DIMM standard 184-pin DIMM lead-free • Frequency/CAS Latency 5ns, 400 MT/s 200 MHz , CL = 3 • PCB 1.25in. 31.75mm MARKING G Y -40B None Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 128MB 4K 4 BA0, BA1 128Mb 16 Meg x 8 1K 1 S0# 256MB 8K 4 BA0, BA1 256Mb 32 Meg x 8 1K 1 S0# 512MB 8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11 1 S0# 2004 Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128MB, 256MB, 512MB x72, ECC, SR , PC3200 184-Pin DDR SDRAM UDIMM Table 2 Part Numbers and Timing Parameters MODULE CONFIGURATION MODULE MEMORY CLOCK/ LATENCY DENSITY BANDWIDTH DATA RATE CL - tRCD - tRP MT9VDDT1672AG-40B__ MT9VDDT1672AY-40B__ MT9VDDT3272AG-40B__ MT9VDDT3272AY-40B__ MT9VDDT6472AG-40B__ MT9VDDT6472AY-40B__ 128MB 256MB 512MB The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 3, or 2 clocks, as shown in Figure 5, CAS Latency Diagram, on page If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 9, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits 128MB , or 256MB, 512MB each set to zero, and bits set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and 128MB , or A7 and 256MB, 512MB each set to zero, bit A8 set to one, and bits set to the desired values. Figure 4 Mode Register Definition Diagram 128MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M13 and M12 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register . 256MB, 512MB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register . M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 Reserved M3 = 1 Reserved Reserved Reserved Reserved Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 3 Reserved M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. 128MB, 256MB, 512MB x72, ECC, SR , PC3200 184-Pin DDR SDRAM UDIMM Table 6 Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED

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128MB, 256MB, 512MB x72, ECC, SR , PC3200 184-Pin DDR SDRAM UDIMM

DDR SDRAM UNBUFFERED DIMM

MT9VDDT1672A 128MB MT9VDDT3272A 256MB MT9VDDT6472A 512MB

For the latest data sheet, please refer to the Web site:
• JEDEC-standard 184-pin dual in-line memory module DIMM
• Fast data transfer rate PC3200
• CAS Latency 3
• Utilizes 400 MT/s DDR SDRAM components
• Supports ECC error detection and correction
• 128MB 16 Meg x 72 , 256MB 32 Meg x 72 , 512MB
64 Meg x 72
• VDD= VDDQ= +2.6V
• VDDSPD = +2.3V to +3.6V
• +2.6V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/
received with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.6µs 128MB , 7.8125µs 256MB, 512MB maximum average periodic refresh interval
• Serial Presence-Detect SPD with EEPROM
• Programmable READ CAS latency
• Gold edge contacts

Figure 1 184-Pin DIMM MO-206

Standard 1.25in. 31.75mm

OPTIONS
• Package 184-pin DIMM standard 184-pin DIMM lead-free
• Frequency/CAS Latency 5ns, 400 MT/s 200 MHz , CL = 3
• PCB 1.25in. 31.75mm

MARKING

G Y -40B None

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
128MB
4K 4 BA0, BA1 128Mb 16 Meg x 8 1K
1 S0#
256MB
8K 4 BA0, BA1 256Mb 32 Meg x 8 1K
1 S0#
512MB
8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11
1 S0#
2004 Micron Technology, Inc.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB, 512MB x72, ECC, SR , PC3200 184-Pin DDR SDRAM UDIMM

Table 2 Part Numbers and Timing Parameters

MODULE CONFIGURATION MODULE MEMORY CLOCK/

LATENCY

DENSITY

BANDWIDTH

DATA RATE

CL - tRCD - tRP

MT9VDDT1672AG-40B__ MT9VDDT1672AY-40B__ MT9VDDT3272AG-40B__ MT9VDDT3272AY-40B__ MT9VDDT6472AG-40B__ MT9VDDT6472AY-40B__
128MB 256MB 512MB
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 3, or 2 clocks, as shown in Figure 5, CAS Latency Diagram, on page

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 9, indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by issuing a MODE REGISTER SET command with bits 128MB , or 256MB, 512MB each set to zero, and bits set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and 128MB , or A7 and 256MB, 512MB each set to zero, bit A8 set to one, and bits set to the desired values.

Figure 4 Mode Register Definition Diagram
128MB Module

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register .
256MB, 512MB Modules

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register .

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

Burst Length

M3 = 0 Reserved

M3 = 1 Reserved

Reserved

Reserved

Reserved

Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 3 Reserved

M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc.
128MB, 256MB, 512MB x72, ECC, SR , PC3200 184-Pin DDR SDRAM UDIMM

Table 6 Burst Definition Table

BURST LENGTH

STARTING COLUMN ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

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Datasheet ID: MT9VDDT6472AY-335F1 648506