MT16LSDT12864AG-13EC1

MT16LSDT12864AG-13EC1 Datasheet

MT8LSDT6464A 512MB MT16LSDT12864A 1GB

Part	Datasheet
MT16LSDT12864AG-13EC1	MT16LSDT12864AG-13EC1 (pdf)

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512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Features Synchronous DRAM Module MT8LSDT6464A 512MB MT16LSDT12864A 1GB For the latest data sheet, refer to Micron’s Web site: • PC100- and PC133-compliant • 168-pin, dual in-line memory module DIMM • Utilizes 125 MHz and 133 MHz SDRAM components • Unbuffered • 512MB 64 Meg x 64 , 1GB 128 Meg x 64 • Single +3.3V power supply • Fully synchronous all signals registered on positive edge of system clock • Internal pipelined operation column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/ precharge • Programmable burst lengths 1, 2, 4, 8, or full page • Auto precharge, including concurrent auto precharge, and auto refresh modes • 64ms, 8,192 cycle auto refresh cycle • Self refresh mode • LVTTL-compatible inputs and outputs • Serial presence-detect SPD • Gold edge contacts Table 1 Timing Parameters Access Time Module Clock Marking Frequency CL = 2 CL = 3 -13E -133 133 MHz 5.4ns 133 MHz 5.4ns Setup Time Hold Time Figure 1 168-Pin DIMM Standard 1.375in. 34.925mm Low Profile 1.125in. 28.575mm Options • Package 168-pin DIMM standard 168-pin DIMM lead-free • Memory Clock/CAS Latency 133 MHz /CL = 2 133 MHz /CL = 3 • PCB Standard 1.375in. 34.93mm Low-Profile 1.125in. 28.58mm Marking -13E -133 See note 1 on page 2 See note 1 on page 2 Notes Contact Micron for product availability. Table 2 Address Table Parameter Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Ranks 512MB 8K 4 BA0, BA1 512Mb 64 Meg x 8 8K 2K A11 1 S0#,S2# 8K 4 BA0, BA1 512Mb 64 Meg x 8 8K 2K A11 2 S0#, S2# S1#, S3# Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Features Table 3 Part Numbers Part Numbers The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6 on page Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. 512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Mode Register Definition Figure 5: Mode Register Definition Diagram A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 12 11 10 9 8 7 Reserved WB Op Mode 6 543 CAS Latency BT 2 10 Burst Length Mode Register Mx Program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. M9 0 1 M2 M1 M0 000 001 010 011 100 101 110 111 Burst Length M3 = 0 1 2 4 8 Reserved Full Page M3 = 1 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 CAS Latency Reserved 2 3 Reserved Operating Mode Defined Standard Operation All Other States Reserved Write Burst Mode Programmed Burst Length Single Location Access Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. 512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Mode Register Definition Table 6 Burst Definition Table Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 8 Full Page n = A11 location 0-y 0-1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit M3. The ordering of the accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 6 on page The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ will start driving after T1 and the data will be valid by T2, as shown in Figure Table 7 on page 12, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. 512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Mode Register Definition Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location non burst accesses. Table 7 CAS Latency Table Speed -13E -133 Allowable Operating Clock Frequency MHz CAS Latency = 2 133 100 CAS Latency = 3 143 133 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. Commands 512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Commands Table 8 provides a quick reference of available commands. This is followed by a written description of each command. For a more detailed description of commands and operations, refer to the 512Mb SDRAM component data sheet. Table 8: Truth Table SDRAM Commands and DQMB Operation CKE is HIGH for all commands shown except SELF REFRESH notes appear following the Truth Table Name Function COMMAND INHIBIT NOP NO OPERATION NOP ACTIVE Select bank and activate row READ Select bank and column, and start READ burst WRITE Select bank and column, and start WRITE burst TERMINATE PRECHARGE Deactivate row in bank or banks AUTO REFRESH or SELF REFRESH Enter self refresh mode LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z CS# RAS# CAS# WE# DQMB ADDR DQ Notes X Bank/Row X H L/H Bank/Col X L/H Bank/Col Valid 2 Active Code X Op-code X Active 7 High-Z 7 Notes provide row address determine which device bank is made active. A11 provide column address A10 HIGH enables the auto-precharge feature nonpersistent , while A10 LOW disables the auto-precharge feature determine which device bank is being read from or written to. A10 LOW determine which device bank is being precharged. A10 HIGH all device banks are precharged and BA0, BA1 are “Don’t Care.” This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing all inputs and I/Os are “Don’t Care” except for CKE. define the op-code written to the mode register and A12 should be driven LOW. Activates or deactivates the DQ during WRITEs zero-clock delay and READs two-clock delay . Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. 512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Absolute Maximum Ratings Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 9 Absolute Maximum DC Ratings Parameter Voltage on VDD, VDDQ supply relative to VSS Voltage on inputs NC or I/O pins relative to VSS Operating temperature TOPR commercial - ambient Storage temperature plastic Min -1 -1 -55 Max +65 +150 Unit V °C °C

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512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Features

Synchronous DRAM Module

MT8LSDT6464A 512MB MT16LSDT12864A 1GB

For the latest data sheet, refer to Micron’s Web site:
• PC100- and PC133-compliant
• 168-pin, dual in-line memory module DIMM
• Utilizes 125 MHz and 133 MHz SDRAM
components
• Unbuffered
• 512MB 64 Meg x 64 , 1GB 128 Meg x 64
• Single +3.3V power supply
• Fully synchronous all signals registered on positive
edge of system clock
• Internal pipelined operation column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths 1, 2, 4, 8, or full page
• Auto precharge, including concurrent auto
precharge, and auto refresh modes
• 64ms, 8,192 cycle auto refresh cycle
• Self refresh mode
• LVTTL-compatible inputs and outputs
• Serial presence-detect SPD
• Gold edge contacts

Table 1 Timing Parameters

Access Time Module Clock Marking Frequency CL = 2 CL = 3
-13E -133
133 MHz 5.4ns
133 MHz
5.4ns

Setup Time

Hold Time

Figure 1 168-Pin DIMM

Standard 1.375in. 34.925mm

Low Profile 1.125in. 28.575mm

Options
• Package 168-pin DIMM standard 168-pin DIMM lead-free
• Memory Clock/CAS Latency 133 MHz /CL = 2 133 MHz /CL = 3
• PCB Standard 1.375in. 34.93mm

Low-Profile 1.125in. 28.58mm

Marking
-13E -133

See note 1 on page 2

See note 1 on page 2

Notes Contact Micron for product availability.

Table 2 Address Table

Parameter Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Ranks
512MB
8K 4 BA0, BA1 512Mb 64 Meg x 8 8K 2K A11 1 S0#,S2#
8K 4 BA0, BA1 512Mb 64 Meg x 8 8K 2K A11 2 S0#, S2# S1#, S3#

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Features

Table 3 Part Numbers

Part Numbers
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6 on page

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.
512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Mode Register Definition

Figure 5:

Mode Register Definition Diagram

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
12 11 10 9 8 7 Reserved WB Op Mode
6 543 CAS Latency BT
2 10 Burst Length

Mode Register Mx

Program M12, M11, M10 = “0, 0, 0”
to ensure compatibility with future devices.

M9 0 1

M2 M1 M0 000 001 010 011 100 101 110 111

Burst Length

M3 = 0 1 2 4 8

Reserved Full Page

M3 = 1 2 4 8

Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1

CAS Latency Reserved 2 3 Reserved

Operating Mode

Defined Standard Operation

All Other States Reserved

Write Burst Mode Programmed Burst Length

Single Location Access

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.
512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Mode Register Definition

Table 6 Burst Definition Table

Burst Length

Starting Column Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
8 Full Page
n = A11 location 0-y
0-1-0
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit M3. The ordering of the accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 6 on page

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ will start driving after T1 and the data will be valid by T2, as shown in Figure Table 7 on page 12, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.
512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Mode Register Definition

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location non burst accesses.

Table 7 CAS Latency Table

Speed -13E -133

Allowable Operating Clock Frequency MHz

CAS Latency = 2 133 100

CAS Latency = 3 143 133

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.

Commands
512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Commands

Table 8 provides a quick reference of available commands. This is followed by a written description of each command. For a more detailed description of commands and operations, refer to the 512Mb SDRAM component data sheet.

Table 8:

Truth Table SDRAM Commands and DQMB Operation CKE is HIGH for all commands shown except SELF REFRESH notes appear following the Truth Table

Name Function

COMMAND INHIBIT NOP NO OPERATION NOP ACTIVE Select bank and activate row READ Select bank and column, and start READ burst WRITE Select bank and column, and start WRITE burst TERMINATE PRECHARGE Deactivate row in bank or banks AUTO REFRESH or SELF REFRESH Enter self refresh mode LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z

CS# RAS# CAS# WE# DQMB ADDR DQ Notes

X Bank/Row X

H L/H Bank/Col X

L/H Bank/Col Valid 2

Active

Code

X Op-code X

Active 7

High-Z 7

Notes provide row address determine which device bank is made active. A11 provide column address A10 HIGH enables the auto-precharge feature nonpersistent , while A10 LOW disables the auto-precharge feature determine which device bank is being read from or written to. A10 LOW determine which device bank is being precharged. A10 HIGH all device banks are precharged and BA0, BA1 are “Don’t Care.” This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing all inputs and I/Os are “Don’t Care” except for CKE. define the op-code written to the mode register and A12 should be driven LOW. Activates or deactivates the DQ during WRITEs zero-clock delay and READs two-clock delay .

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.
512MB SR , 1GB DR x64 168-Pin SDRAM UDIMM Absolute Maximum Ratings

Absolute Maximum Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Table 9 Absolute Maximum DC Ratings

Parameter Voltage on VDD, VDDQ supply relative to VSS Voltage on inputs NC or I/O pins relative to VSS Operating temperature TOPR commercial - ambient Storage temperature plastic

Min -1 -1 -55

Max +65 +150

Unit V °C °C

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Datasheet ID: MT16LSDT12864AG-13EC1 648485