MT49H16M16FM-5 TR

MT49H16M16FM-5 TR Datasheet

MT49H8M32 1 Meg x 32 x 8 banks MT49H16M16 2 Meg x 16 x 8 banks

Part	Datasheet
MT49H16M16FM-5 TR	MT49H16M16FM-5 TR (pdf)

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256Mb x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM Features REDUCED LATENCY DRAM MT49H8M32 1 Meg x 32 x 8 banks MT49H16M16 2 Meg x 16 x 8 banks For the latest data sheet, refer to Micron’s Web site: • Organization 8 Meg x 32, 16 Meg x 16 in 8 banks • Cyclic bank addressing for maximum data bandwidth • Non multiplexed addresses • Non interruptible sequential burst of two 2-bit prefetch and four 4-bit prefetch DDR • Up to 600 Mb/sec/pin data rate • Programmable READ latency RL of 5-6 • Data valid signal DVLD activated as read data is available • Data mask signals DM0/DM1 to mask first and • second part of write data burst • IEEE compliant JTAG boundary scan • 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O • Pseudo-HSTL 1.8V I/O Supply • Internal auto precharge • Refresh requirements 32ms at 95°C case temperature 8K refresh for each bank, 64K refresh command must be issued in total each 32ms • 144-pin, 11mm x 18.5mm µBGA package Options • Clock Cycle Timing 3.3ns 300 MHz 4ns 250 MHz 5ns 200 MHz • Configuration 8 Meg x 32 1 Meg x 32 x 8 banks 16 Meg x 16 2 Meg x 16 x 8 banks • Operating temperature range Commercial 0° to +95°C Industrial TC = -40°C to +95°C TA = -40°C to 85°C • Package 144-ball, 11mm x 18.5mm µBGA Standard 144-ball, 11mm x 18.5mm µBGA Lead-Free Marking -33 -4 -5 MT49H8M32 MT49H16M16 None IT FM BM1 Notes Contact factory for availability. Figure 1 144-Ball µBGA Table 1 Valid Part Numbers Part Number MT49H8M32FM-xx MT49H16M16FM-xx Description 8 Meg x 32 16 Meg x 16 The 256Mb reduced latency DRAM contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate DDR form at where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth. RLDRAM is designed for high bandwidth communication data networking, and cache applications, etc. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 256Mb x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM Table of Contents Table of Contents Features Options General Description Functional Block Diagrams Ball Assignment and Description Commands Initialization Mode Register Set Command MRS . Configuration Table Write Basic Information. Read Basic Information AUTO REFRESH Command AREF IEEE Serial Boundary Scan JTAG Disabling The JTAG Feature Test Access Port TAP Test Clock TCK Test Mode Select TMS Test Data-in TDI Test Data-out TDO Performing A Tap RESET Tap Registers Instruction Register Bypass Register Boundary Scan Register Identification Id Register Tap Instruction Set Overview. EXTEST IDCODE SAMPLE/PRELOAD BYPASS Reserved for Future Use Electrical Characteristics Recommended DC Operation Ranges Package Dimensions Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001 Micron Technology, Inc. All rights reserved. 256Mb x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM List of Figures List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32: 144-Ball µBGA 8 Meg x 32 16 Meg x 16 Clock Command/Address Timings Power-Up Sequence. Clock Input. Mode Register Set Mode Register Set Timing Mode Register Bit Map WRITE Command Basic WRITE Burst Timing WRITE Burst Basic Sequence BL = 2 WL = 3 WRITE Burst Basic Sequence BL = 4 WL = 2 WRITE Data Mask Timing BL = 2 WL = 2 Write Data Mask Timing BL = 4 WL = 1 WRITE followed by READ BL = 4 RL = 5 WL = 1 READ Command Basic READ Burst Timing READ Burst BL = 2 RL = 5 READ Burst BL = 4 RL = 5 READ followed by WRITE BL = 2 RL = 5 WL = 2 READ followed by WRITE BL = 2 RL = 5 WL = 2 Interleaved Data READ followed by WRITE BL = 4 RL = 5 WL = 1 READ followed by WRITE BL = 4 RL = 5 WL = 1 Interleaved Data AUTO REFRESH Command AUTO REFRESH Cycle TAP Controller State Diagram TAP Controller Block Diagram TAP Timing. Absolute Maximum Ratings Output Test Conditions 144-Ball µBGA Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001 Micron Technology, Inc. All rights reserved. 256Mb x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM List of Tables

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256Mb x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM Features

REDUCED LATENCY DRAM

MT49H8M32 1 Meg x 32 x 8 banks MT49H16M16 2 Meg x 16 x 8 banks

For the latest data sheet, refer to Micron’s Web site:
• Organization 8 Meg x 32, 16 Meg x 16 in 8 banks
• Cyclic bank addressing for maximum data
bandwidth
• Non multiplexed addresses
• Non interruptible sequential burst of two 2-bit
prefetch and four 4-bit prefetch DDR
• Up to 600 Mb/sec/pin data rate
• Programmable READ latency RL of 5-6
• Data valid signal DVLD activated as read data is
available
• Data mask signals DM0/DM1 to mask first and
• second part of write data burst
• IEEE compliant JTAG boundary scan
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Pseudo-HSTL 1.8V I/O Supply
• Internal auto precharge
• Refresh requirements 32ms at 95°C case
temperature 8K refresh for each bank, 64K refresh command must be issued in total each 32ms
• 144-pin, 11mm x 18.5mm µBGA package

Options
• Clock Cycle Timing 3.3ns 300 MHz 4ns 250 MHz 5ns 200 MHz
• Configuration 8 Meg x 32 1 Meg x 32 x 8 banks 16 Meg x 16 2 Meg x 16 x 8 banks
• Operating temperature range Commercial 0° to +95°C Industrial TC = -40°C to +95°C TA = -40°C to 85°C
• Package 144-ball, 11mm x 18.5mm µBGA Standard 144-ball, 11mm x 18.5mm µBGA Lead-Free

Marking
-33 -4 -5

MT49H8M32 MT49H16M16

None IT

FM BM1

Notes Contact factory for availability.

Figure 1 144-Ball µBGA

Table 1 Valid Part Numbers

Part Number MT49H8M32FM-xx MT49H16M16FM-xx

Description 8 Meg x 32
16 Meg x 16

The 256Mb reduced latency DRAM contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate DDR form at where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.

RLDRAM is designed for high bandwidth communication data networking, and cache applications, etc.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
256Mb x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM Table of Contents

Table of Contents

Features Options

General Description Functional Block Diagrams Ball Assignment and Description Commands Initialization Mode Register Set Command MRS . Configuration Table Write Basic Information. Read Basic Information AUTO REFRESH Command AREF IEEE Serial Boundary Scan JTAG Disabling The JTAG Feature Test Access Port TAP

Test Clock TCK Test Mode Select TMS Test Data-in TDI Test Data-out TDO Performing A Tap RESET Tap Registers Instruction Register Bypass Register Boundary Scan Register Identification Id Register Tap Instruction Set Overview. EXTEST IDCODE SAMPLE/PRELOAD BYPASS Reserved for Future Use Electrical Characteristics Recommended DC Operation Ranges Package Dimensions

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001 Micron Technology, Inc. All rights reserved.
256Mb x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM List of Figures

List of Figures

Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32:
144-Ball µBGA 8 Meg x 32 16 Meg x 16 Clock Command/Address Timings Power-Up Sequence. Clock Input. Mode Register Set Mode Register Set Timing Mode Register Bit Map WRITE Command Basic WRITE Burst Timing WRITE Burst Basic Sequence BL = 2 WL = 3 WRITE Burst Basic Sequence BL = 4 WL = 2 WRITE Data Mask Timing BL = 2 WL = 2 Write Data Mask Timing BL = 4 WL = 1 WRITE followed by READ BL = 4 RL = 5 WL = 1 READ Command Basic READ Burst Timing READ Burst BL = 2 RL = 5 READ Burst BL = 4 RL = 5 READ followed by WRITE BL = 2 RL = 5 WL = 2 READ followed by WRITE BL = 2 RL = 5 WL = 2 Interleaved Data READ followed by WRITE BL = 4 RL = 5 WL = 1 READ followed by WRITE BL = 4 RL = 5 WL = 1 Interleaved Data AUTO REFRESH Command AUTO REFRESH Cycle TAP Controller State Diagram TAP Controller Block Diagram TAP Timing. Absolute Maximum Ratings Output Test Conditions 144-Ball µBGA

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001 Micron Technology, Inc. All rights reserved.
256Mb x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM List of Tables

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT49H16M16FM-5TR Datasheet file may be downloaded here without warranties.

Datasheet ID: MT49H16M16FM-5TR 648469