MT48H4M16LFB4-8 IT TR

MT48H4M16LFB4-8 IT TR Datasheet

MT48H4M16LF - 1 MEG x 16 x 4 BANKS

Part	Datasheet
MT48H4M16LFB4-8 IT TR	MT48H4M16LFB4-8 IT TR (pdf)

Related Parts	Information
MT48H4M16LFB4-8 TR	MT48H4M16LFB4-8 TR
MT48H4M16LFB4-8 IT	MT48H4M16LFB4-8 IT
MT48H4M16LFB4-10 IT TR	MT48H4M16LFB4-10 IT TR
MT48H4M16LFF4-10 TR	MT48H4M16LFF4-10 TR
MT48H4M16LFF4-10	MT48H4M16LFF4-10
MT48H4M16LFB4-10	MT48H4M16LFB4-10
MT48H4M16LFB4-10 IT	MT48H4M16LFB4-10 IT
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MT48H4M16LFB4-8	MT48H4M16LFB4-8
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SYNCHRONOUS DRAM 64Mb x16 MOBILE SDRAM MT48H4M16LF - 1 MEG x 16 x 4 BANKS • Temperature compensated self refresh TCSR • Fully synchronous all signals registered on positive edge of system clock • Internal pipelined operation column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths 1, 2, 4, 8, or full page • Auto Precharge, includes concurrent auto precharge, and auto refresh modes • Self refresh mode standard and low power • 64ms, 4,096-cycle refresh • LVTTL-compatible inputs and outputs • Low voltage power supply • Partial array self refresh power-saving mode • Deep power-down mode • Programmable output drive strength • Operating temperature ranges: Extended -25°C to +85°C Industrial -40°C to +85°C OPTIONS • VDD/VDDQ 1.8V/1.8V • Configurations 4 Meg x 16 1 Meg x 16 x 4 banks • Package/Ball out 54-ball FBGA, 8mm x 8mm standard 54-ball FBGA, 8mm x 8mm lead-free • Timing Cycle Time 8ns CL = 3 125 MHz 9.6ns CL = 3 104 MHz • Operating Temperature Extended -25°C to +85°C Industrial -40°C to +85°C MARKING 4M16 F4 B4 -8 -10 none IT FBGA Part Number System Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on the Micron web site, Figure 1 54-Ball FBGA Pin Assignment Top View DQ15 VSSQ VDDQ DQ0 DQ14 DQ13 VDDQ VSSQ DQ12 DQ11 VSSQ VDDQ DQ4 DQ10 DQ9 VDDQ VSSQ VDD LDQM DQ7 F UDQM CLK CAS# RAS# WE# G NC/A12 A11 Top View Ball Down Table 1 Address Table Configuration Refresh Count Row Addressing Bank Addressing Column Addressing 4 MEG x 16 1 Meg x 16 x 4 banks 4K 4K 4 BA0, BA1 256 Table 2 Key Timing Parameters The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 5, CAS Latency. Table 5, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 5 CAS Latency COMMAND DQ READ NOP tLZ tAC CASLatency = 2 NOP tOH DOUT CLK COMMAND T0 READ NOP tLZ tAC CASLatency = 3 NOP tOH DOUT DON’T CARE UNDEFINED 64Mb x16 MOBILE SDRAM Table 5 CAS Latency SPEED -8 -10 ALLOWABLE OPERATING FREQUENCY MHZ CAS LATENCY = 2 CAS LATENCY = 3 125 104 Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both read and write bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location nonburst accesses. Extended Mode Register The extended mode register controls the functions beyond those controlled by the mode register. These additional functions are special features of the mobile device. They include temperature compensated self refresh TCSR control, partial array self refresh PASR , and output drive strength. Not programming the extended mode register upon initialization, will result in default settings for the low power features. The extended mode will default to the +85°C setting for TCSR, full drive strength, and full array refresh. The extended mode register is programmed via the MODE REGISTER SET command BA1 = 1, BA0 = 0 and retains the stored information until it is programmed again or the device loses power. The extended mode register must be programmed with E6 through E11 set to It must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. Once the values are entered the extended mode register settings will be retained even after exiting deep power-down. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. Temperature Compensated Self Refresh Temperature compensated self refresh TCSR allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the mobile device. This allows great power savings during SELF REFRESH during most operating temperature ranges. Only during extreme temperatures would the controller have to select the maximum TCSR level. This would guarantee data during SELF REFRESH. Every cell in the SDRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. Historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected. Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. Adjusting the refresh rate by setting E4 and E3 allows the SDRAM to accommodate more specific temperature regions during SELF REFRESH. There are four temperature settings, which will vary the SELF REFRESH current according to the selected temperature. This selectable refresh rate will save power when the SDRAM is operating at normal temperatures. Partial Array Self Refresh

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SYNCHRONOUS DRAM
64Mb x16 MOBILE SDRAM

MT48H4M16LF - 1 MEG x 16 x 4 BANKS
• Temperature compensated self refresh TCSR
• Fully synchronous all signals registered on positive
edge of system clock
• Internal pipelined operation column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths 1, 2, 4, 8, or full page
• Auto Precharge, includes concurrent auto
precharge, and auto refresh modes
• Self refresh mode standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Partial array self refresh power-saving mode
• Deep power-down mode
• Programmable output drive strength
• Operating temperature ranges:

Extended -25°C to +85°C Industrial -40°C to +85°C

OPTIONS
• VDD/VDDQ 1.8V/1.8V
• Configurations 4 Meg x 16 1 Meg x 16 x 4 banks
• Package/Ball out 54-ball FBGA, 8mm x 8mm standard 54-ball FBGA, 8mm x 8mm lead-free
• Timing Cycle Time 8ns CL = 3 125 MHz 9.6ns CL = 3 104 MHz
• Operating Temperature Extended -25°C to +85°C Industrial -40°C to +85°C

MARKING
4M16

F4 B4
-8 -10
none IT

FBGA Part Number System

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on the Micron web site,

Figure 1 54-Ball FBGA Pin Assignment Top View

DQ15 VSSQ

VDDQ DQ0

DQ14 DQ13 VDDQ

VSSQ

DQ12 DQ11 VSSQ

VDDQ DQ4

DQ10 DQ9 VDDQ

VSSQ

VDD LDQM DQ7

F UDQM CLK

CAS# RAS# WE#

G NC/A12 A11

Top View Ball Down

Table 1 Address Table

Configuration Refresh Count Row Addressing Bank Addressing Column Addressing
4 MEG x 16
1 Meg x 16 x 4 banks 4K
4K 4 BA0, BA1 256

Table 2 Key Timing Parameters
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.

CAS Latency

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 5, CAS Latency. Table 5, indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Figure 5 CAS Latency

COMMAND DQ

READ

NOP tLZ
tAC CASLatency = 2

NOP tOH DOUT

CLK COMMAND

T0 READ

NOP tLZ
tAC CASLatency = 3

NOP tOH DOUT

DON’T CARE UNDEFINED
64Mb x16 MOBILE SDRAM

Table 5 CAS Latency

SPEED -8 -10

ALLOWABLE OPERATING FREQUENCY MHZ

CAS LATENCY = 2

CAS LATENCY = 3
125 104

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both read and write bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location nonburst accesses.

Extended Mode Register

The extended mode register controls the functions beyond those controlled by the mode register. These additional functions are special features of the mobile device. They include temperature compensated self refresh TCSR control, partial array self refresh PASR , and output drive strength. Not programming the extended mode register upon initialization, will result in default settings for the low power features. The extended mode will default to the +85°C setting for TCSR, full drive strength, and full array refresh.

The extended mode register is programmed via the MODE REGISTER SET command BA1 = 1, BA0 = 0 and retains the stored information until it is programmed again or the device loses power.

The extended mode register must be programmed with E6 through E11 set to It must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation.

Once the values are entered the extended mode register settings will be retained even after exiting deep power-down.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.

Temperature Compensated Self Refresh

Temperature compensated self refresh TCSR allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the mobile device. This allows great power savings during SELF REFRESH during most operating temperature ranges. Only during extreme temperatures would the controller have to select the maximum TCSR level. This would guarantee data during SELF REFRESH.

Every cell in the SDRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. Historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected.

Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. Adjusting the refresh rate by setting E4 and E3 allows the SDRAM to accommodate more specific temperature regions during SELF REFRESH. There are four temperature settings, which will vary the SELF REFRESH current according to the selected temperature. This selectable refresh rate will save power when the SDRAM is operating at normal temperatures.

Partial Array Self Refresh

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Datasheet ID: MT48H4M16LFB4-8ITTR 648465