MT48H8M32LFB5-75 AT:H

MT48H8M32LFB5-75 AT:H Datasheet

MT48H16M16LF 4 Meg x 16 x 4 banks MT48H8M32LF 2 Meg x 32 x 4 banks

Part	Datasheet
MT48H8M32LFB5-75 AT:H	MT48H8M32LFB5-75 AT:H (pdf)

Related Parts	Information
MT48H16M16LFBF-75 IT:H	MT48H16M16LFBF-75 IT:H
MT48H8M32LFB5-6 IT:H	MT48H8M32LFB5-6 IT:H
MT48H16M16LFBF-6 IT:H	MT48H16M16LFBF-6 IT:H
MT48H16M16LFBF-6:H	MT48H16M16LFBF-6:H

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256Mb 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Features Mobile Low-Power SDR SDRAM MT48H16M16LF 4 Meg x 16 x 4 banks MT48H8M32LF 2 Meg x 32 x 4 banks • VDD/VDDQ = • Fully synchronous all signals registered on positive edge of system clock • Internal, pipelined operation column address can be changed every clock cycle • Four internal banks for concurrent operation • Programmable burst lengths 1, 2, 4, 8, and continu- ous • Auto precharge, includes concurrent auto precharge • Auto refresh and self refresh modes • LVTTL-compatible inputs and outputs • On-chip temperature sensor to control self refresh rate • Partial-array self refresh PASR • Deep power-down DPD • Selectable output drive strength DS • 64ms refresh period Options • VDD/VDDQ 1.8V/1.8V • Addressing Standard addressing option • Configuration Marking 16M16 8M32 BF B5 -6 -75 None IT :H Notes Available only for x16 configuration. Available only for x32 configuration. Table 1 Configuration Addressing Architecture Number of banks Bank address balls Row address balls Column address balls 16 Meg x 16 4 BA0, BA1 A[12:0] A[8:0] 8 Meg x 32 4 BA0, BA1 A[11:0] A[8:0] Table 2 Key Timing Parameters Speed Grade Clock Rate MHz CL = 2 CL = 3 Access Time CL = 2 CL = 3 8.0ns 5.0ns 8.0ns 5.4ns Note CL = CAS READ latency Micron Technology, Inc. reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 256Mb 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Features Figure 1 256Mb Mobile LPSDR Part Numbering MT 48 H 16M16 LF BF -6 IT :H Micron Technology Product Family 48 = Mobile SDR SDRAM The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved. 256Mb 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Mode Register Table 19 Burst Definition Table Burst Length 2 4 8 Continuous Starting Column Address n = location Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1, Cn... Not supported Micron Technology, Inc. reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved. 256Mb 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Mode Register CAS Latency The CAS latency CL is the delay, in clock cycles, between the registration of a READ command and the availability of the output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data is valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ start driving after T1 and the data is valid by T2. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 14 CAS Latency Command DQ READ NOP tLZ NOP tOH DOUT CL = 2 Command READ NOP tLZ tAC CL = 3 NOP tOH DOUT Don’t Care Undefined Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use. Reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode

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256Mb 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Features

Mobile Low-Power SDR SDRAM

MT48H16M16LF 4 Meg x 16 x 4 banks MT48H8M32LF 2 Meg x 32 x 4 banks
• VDD/VDDQ =
• Fully synchronous all signals registered on positive
edge of system clock
• Internal, pipelined operation column address can
be changed every clock cycle
• Four internal banks for concurrent operation
• Programmable burst lengths 1, 2, 4, 8, and continu-
ous
• Auto precharge, includes concurrent auto precharge
• Auto refresh and self refresh modes
• LVTTL-compatible inputs and outputs
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh PASR
• Deep power-down DPD
• Selectable output drive strength DS
• 64ms refresh period

Options
• VDD/VDDQ 1.8V/1.8V
• Addressing

Standard addressing option
• Configuration

Marking
16M16 8M32

BF B5
-6 -75

None IT :H

Notes Available only for x16 configuration. Available only for x32 configuration.

Table 1 Configuration Addressing

Architecture Number of banks Bank address balls Row address balls Column address balls
16 Meg x 16 4

BA0, BA1 A[12:0] A[8:0]
8 Meg x 32 4

BA0, BA1 A[11:0] A[8:0]

Table 2 Key Timing Parameters

Speed Grade

Clock Rate MHz

CL = 2 CL = 3

Access Time

CL = 2 CL = 3
8.0ns
5.0ns
8.0ns
5.4ns

Note CL = CAS READ latency

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
256Mb 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Features

Figure 1 256Mb Mobile LPSDR Part Numbering MT 48 H 16M16 LF BF -6 IT :H

Micron Technology

Product Family
48 = Mobile SDR SDRAM
The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
256Mb 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Mode Register

Table 19 Burst Definition Table

Burst Length 2 4 8

Continuous

Starting Column Address
n = location

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3 1-0-3-2-3-0-1 3-2-1-0
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0

Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1, Cn...

Not supported

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
256Mb 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Mode Register

CAS Latency

The CAS latency CL is the delay, in clock cycles, between the registration of a READ command and the availability of the output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data is valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ start driving after T1 and the data is valid by T2.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Figure 14 CAS Latency

Command DQ

READ

NOP tLZ

NOP tOH

DOUT

CL = 2

Command

READ

NOP tLZ
tAC CL = 3

NOP tOH

DOUT

Don’t Care

Undefined

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use. Reserved states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

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Datasheet ID: MT48H8M32LFB5-75AT:H 648462