MT47H64M8B6-3:D TR

MT47H64M8B6-3:D TR Datasheet

MT47H128M4 32 Meg x 4 x 4 Banks MT47H64M8 16 Meg x 8 x 4 Banks MT47H32M16 8 Meg x 16 x 4 Banks

Part	Datasheet
MT47H64M8B6-3:D TR	MT47H64M8B6-3:D TR (pdf)

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DDR2 SDRAM MT47H128M4 32 Meg x 4 x 4 Banks MT47H64M8 16 Meg x 8 x 4 Banks MT47H32M16 8 Meg x 16 x 4 Banks 512Mb x4, x8, x16 DDR2 SDRAM Features • RoHS compliant • VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V • JEDEC-standard 1.8V I/O SSTL_18-compatible • Differential data strobe DQS, DQS# option • 4n-bit prefetch architecture • Duplicate output strobe RDQS option for x8 • DLL to align DQ and DQS transitions with CK • 4 internal banks for concurrent operation • Programmable CAS latency CL • Posted CAS additive latency AL • WRITE latency = READ latency - 1 tCK • Selectable burst lengths BL 4 or 8 • Adjustable data-output drive strength • 64ms, 8,192-cycle refresh • On-die termination ODT • Industrial temperature IT option • Automotive temperature AT option • Supports JEDEC clock jitter specification Options Marking • Configuration 128 Meg x 4 32 Meg x 4 x 4 banks 128M4 64 Meg x 8 16 Meg x 8 x 4 banks 64M8 32 Meg x 16 8 Meg x 16 x 4 banks 32M16 • FBGA package Pb-free • FBGA package with lead • Timing cycle time 2.5ns CL = 5 DDR2-800 -25E 2.5ns CL = 6 DDR2-800 3.0ns CL = 4 DDR2-667 3.0ns CL = 5 DDR2-667 3.75ns CL = 4 DDR2-533 5.0ns CL = 3 DDR2-400 -3 -37E1 -5E1 • Self refresh Standard None Low-power • Operating temperature Commercial 0°C TC 85°C Industrial TC 95°C; TA 85°C None IT :B1/:D1/:F Notes Not recommended for new designs Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512Mb x4, x8, x16 DDR2 SDRAM Features Table 1 Key Timing Parameters Speed Grade -25E -25 -3E -3 -37E -5E CL = 3 CL = 4 533 667 533 400 Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3, as shown in Figure The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 40 on page DDR2 SDRAM supports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleaved address ordering is supported however, sequential address ordering is nibble-based. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 512Mb x4, x8, x16 DDR2 SDRAM Operations Table 40 Burst Definition Burst Length 4 Starting Column Address A2, A1, A0 00 01 10 11 000 001 010 011 100 101 110 111 Order of Accesses Within a Burst Burst Type = Sequential 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 Burst Type = Interleaved 0, 1, 2, 3 1, 0, 3, 2, 3, 0, 1 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Operating Mode The normal operating mode is selected by issuing a command with bit M7 set to “0,” and all other bits set to the desired values, as shown in Figure 39 on page When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is DLL RESET DLL RESET is defined by bit M8, as shown in Figure 39 on page Programming bit M8 to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of “0” after the DLL RESET function has been issued. Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Write Recovery Write recovery WR time is defined by bits as shown in Figure 39 on page The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge operation, the DDR2 SDRAM delays the internal auto precharge operation by WR clocks programmed in bits from the last data burst. An example of WRITE with auto precharge is shown in Figure 67 on page WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits The user is required to program the value of WR, which is calculated by dividing tWR in nanoseconds by tCK in nanoseconds and rounding up a noninteger value to the next integer WR cycles = tWR ns /tCK ns . Reserved states should not be used as an unknown operation or incompatibility with future versions may result. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 512Mb x4, x8, x16 DDR2 SDRAM Operations Power-Down Mode CAS Latency CL Active power-down PD mode is defined by bit M12, as shown in Figure 39 on page PD mode allows the user to determine the active power-down mode, which determines performance versus power savings. PD mode bit M12 does not apply to precharge PD mode. When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled. The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to be enabled and running during this mode. When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is enabled. The tXARDS parameter is used for slow-exit active PD exit timing. The DLL can be enabled but “frozen” during active PD mode because the exit-to-READ command timing is relaxed. The power difference expected between IDD3P normal and IDD3P lowpower mode is defined in Table 11 on page The CAS latency CL is defined by bits as shown in Figure 39 on page CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending on the speed grade option being used. DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be used as an unknown operation otherwise incompatibility with future versions may result. DDR2 SDRAM also supports a feature called posted CAS additive latency AL . This feature allows the READ command to be issued prior to tRCD MIN by delaying the internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further detail in “Posted CAS Additive Latency AL ” on page Examples of CL = 3 and CL = 4 are shown in Figure 40 on page 77 both assume AL = If a READ command is registered at clock edge n, and the CL is m clocks, the data will be available nominally coincident with clock edge n + m this assumes AL = Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. Figure 40 CAS Latency CL Command READ DQS, DQS# DQ CL = 3 AL = 0 CK# CK Command DQS, DQS# T0 READ

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DDR2 SDRAM

MT47H128M4 32 Meg x 4 x 4 Banks MT47H64M8 16 Meg x 8 x 4 Banks MT47H32M16 8 Meg x 16 x 4 Banks
512Mb x4, x8, x16 DDR2 SDRAM Features
• RoHS compliant
• VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
• JEDEC-standard 1.8V I/O SSTL_18-compatible
• Differential data strobe DQS, DQS# option
• 4n-bit prefetch architecture
• Duplicate output strobe RDQS option for x8
• DLL to align DQ and DQS transitions with CK
• 4 internal banks for concurrent operation
• Programmable CAS latency CL
• Posted CAS additive latency AL
• WRITE latency = READ latency - 1 tCK
• Selectable burst lengths BL 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination ODT
• Industrial temperature IT option
• Automotive temperature AT option
• Supports JEDEC clock jitter specification

Options

Marking
• Configuration
128 Meg x 4 32 Meg x 4 x 4 banks
128M4
64 Meg x 8 16 Meg x 8 x 4 banks
64M8
32 Meg x 16 8 Meg x 16 x 4 banks
32M16
• FBGA package Pb-free
• FBGA package with lead
• Timing cycle time
2.5ns CL = 5 DDR2-800
-25E
2.5ns CL = 6 DDR2-800
3.0ns CL = 4 DDR2-667
3.0ns CL = 5 DDR2-667 3.75ns CL = 4 DDR2-533 5.0ns CL = 3 DDR2-400
-3 -37E1 -5E1
• Self refresh

Standard

None

Low-power
• Operating temperature

Commercial 0°C TC 85°C Industrial TC 95°C;

TA 85°C

None IT
:B1/:D1/:F

Notes Not recommended for new designs

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
512Mb x4, x8, x16 DDR2 SDRAM Features

Table 1 Key Timing Parameters

Speed Grade
-25E -25 -3E -3 -37E -5E

CL = 3

CL = 4
533 667 533 400
Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3, as shown in Figure The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 40 on page DDR2 SDRAM supports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleaved address ordering is supported however, sequential address ordering is nibble-based.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
512Mb x4, x8, x16 DDR2 SDRAM Operations

Table 40 Burst Definition

Burst Length 4

Starting Column Address

A2, A1, A0
00 01 10 11 000 001 010 011 100 101 110 111

Order of Accesses Within a Burst

Burst Type = Sequential
0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2

Burst Type = Interleaved
0, 1, 2, 3 1, 0, 3, 2, 3, 0, 1 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0

Operating Mode

The normal operating mode is selected by issuing a command with bit M7 set to “0,” and all other bits set to the desired values, as shown in Figure 39 on page When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is

DLL RESET

DLL RESET is defined by bit M8, as shown in Figure 39 on page Programming bit M8 to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of “0” after the DLL RESET function has been issued.

Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.

Write Recovery

Write recovery WR time is defined by bits as shown in Figure 39 on page The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge operation, the DDR2 SDRAM delays the internal auto precharge operation by WR clocks programmed in bits from the last data burst. An example of WRITE with auto precharge is shown in Figure 67 on page

WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits The user is required to program the value of WR, which is calculated by dividing tWR in nanoseconds by tCK in nanoseconds and rounding up a noninteger value to the next integer WR cycles = tWR ns /tCK ns . Reserved states should not be used as an unknown operation or incompatibility with future versions may result.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
512Mb x4, x8, x16 DDR2 SDRAM Operations

Power-Down Mode CAS Latency CL

Active power-down PD mode is defined by bit M12, as shown in Figure 39 on page PD mode allows the user to determine the active power-down mode, which determines performance versus power savings. PD mode bit M12 does not apply to precharge PD mode.

When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled. The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to be enabled and running during this mode.

When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is enabled. The tXARDS parameter is used for slow-exit active PD exit timing. The DLL can be enabled but “frozen” during active PD mode because the exit-to-READ command timing is relaxed. The power difference expected between IDD3P normal and IDD3P lowpower mode is defined in Table 11 on page

The CAS latency CL is defined by bits as shown in Figure 39 on page CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending on the speed grade option being used.

DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be used as an unknown operation otherwise incompatibility with future versions may result.

DDR2 SDRAM also supports a feature called posted CAS additive latency AL . This feature allows the READ command to be issued prior to tRCD MIN by delaying the internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further detail in “Posted CAS Additive Latency AL ” on page

Examples of CL = 3 and CL = 4 are shown in Figure 40 on page 77 both assume AL = If a READ command is registered at clock edge n, and the CL is m clocks, the data will be available nominally coincident with clock edge n + m this assumes AL =

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.

Figure 40 CAS Latency CL

Command

READ

DQS, DQS#

DQ CL = 3 AL = 0

CK# CK

Command

DQS, DQS#

T0 READ

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Datasheet ID: MT47H64M8B6-3:DTR 648450