MT46H256M32L4SA-48 WT:C TR

MT46H256M32L4SA-48 WT:C TR Datasheet

MT46H128M16LF 32 Meg x 16 x 4 Banks MT46H64M32LF 16 Meg x 32 x 4 Banks MT46H128M32L2 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 32 Meg x 16 x 4 Banks x 4

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MT46H256M32L4SA-48 WT:C TR	MT46H256M32L4SA-48 WT:C TR (pdf)

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MT46H256M32L4SA-48 WT:C	MT46H256M32L4SA-48 WT:C

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2Gb x16, x32 Automotive LPDDR SDRAM Features Automotive LPDDR SDRAM MT46H128M16LF 32 Meg x 16 x 4 Banks MT46H64M32LF 16 Meg x 32 x 4 Banks MT46H128M32L2 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 32 Meg x 16 x 4 Banks x 4 • VDD/VDDQ = • Bidirectional data strobe per byte of data DQS • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Differential clock inputs CK and CK# • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • 4 internal banks for concurrent operation • Data masks DM for masking write data one mask per byte • Programmable burst lengths BL 2, 4, 8, or 16 • Concurrent auto precharge option is supported • Auto refresh and self refresh modes • 1.8V LVCMOS-compatible inputs • Temperature-compensated self refresh TCSR 2 • Partial-array self refresh PASR • Deep power-down DPD • Status read register SRR • Selectable output drive strength DS • Clock stop capability • 64ms refresh 32ms for the automotive temperature range Table 1 Key Timing Parameters CL = 3 Speed Grade -48 -5 Clock Rate 208 MHz 200 MHz Access Time 4.8ns 5.0ns Options Mark • VDD/VDDQ 1.8V/1.8V • Configuration 256 Meg x 32 Meg x 16 x 4 banks x 256M32 128 Meg x 32 16 Meg x 32 x 4 banks x 128M32 128 Meg x 16 32 Meg x 16 x 4 banks 128M16 64 Meg x 32 16 Meg x 32 x 4 banks 64M32 • Addressing JEDEC-standard 2-die stack standard 4-die stack standard • Plastic "green" package 60-ball VFBGA 8mm x 9mm 90-ball VFBGA 8mm x 13mm • PoP plastic "green" package 168-ball WFBGA DDP 12mm x 12mm 168-ball TFBGA QDP 12mm x 12mm • Timing cycle time 4.8ns CL = 3 208 MHz 5ns CL = 3 200 MHz • Special Options None Automotive package-level burn-in • Operating temperature range From to The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. Table 21 Burst Definition Table Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved. 2Gb x16, x32 Automotive LPDDR SDRAM Standard Mode Register Table 21 Burst Definition Table Continued Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6 A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5

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2Gb x16, x32 Automotive LPDDR SDRAM Features

Automotive LPDDR SDRAM

MT46H128M16LF 32 Meg x 16 x 4 Banks MT46H64M32LF 16 Meg x 32 x 4 Banks MT46H128M32L2 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 32 Meg x 16 x 4 Banks x 4
• VDD/VDDQ =
• Bidirectional data strobe per byte of data DQS
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Differential clock inputs CK and CK#
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks DM for masking write data one mask
per byte
• Programmable burst lengths BL 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• Temperature-compensated self refresh TCSR 2
• Partial-array self refresh PASR
• Deep power-down DPD
• Status read register SRR
• Selectable output drive strength DS
• Clock stop capability
• 64ms refresh 32ms for the automotive temperature
range

Table 1 Key Timing Parameters CL = 3

Speed Grade -48 -5

Clock Rate 208 MHz 200 MHz

Access Time 4.8ns 5.0ns

Options

Mark
• VDD/VDDQ
1.8V/1.8V
• Configuration
256 Meg x 32 Meg x 16 x 4 banks x 256M32
128 Meg x 32 16 Meg x 32 x 4 banks x 128M32
128 Meg x 16 32 Meg x 16 x 4 banks 128M16
64 Meg x 32 16 Meg x 32 x 4 banks 64M32
• Addressing

JEDEC-standard
2-die stack standard
4-die stack standard
• Plastic "green" package
60-ball VFBGA 8mm x 9mm
90-ball VFBGA 8mm x 13mm
• PoP plastic "green" package
168-ball WFBGA DDP 12mm x
12mm
168-ball TFBGA QDP 12mm x
12mm
• Timing cycle time
4.8ns CL = 3 208 MHz
5ns CL = 3 200 MHz
• Special Options

None

Automotive package-level burn-in
• Operating temperature range

From to
The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address.

Table 21 Burst Definition Table

Burst Length

Starting Column Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3 1-0-3-2-3-0-1 3-2-1-0
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved.
2Gb x16, x32 Automotive LPDDR SDRAM Standard Mode Register

Table 21 Burst Definition Table Continued

Burst Length

Starting Column Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0
1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E
2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1
2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D
3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2
3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C
4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3
4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B
5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4
5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A
6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5
6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9
7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8
9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6

A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9

A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5

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Datasheet ID: MT46H256M32L4SA-48WT:CTR 648442