IDT70P3517S233RM

IDT70P3517S233RM Datasheet

PRELIMINARY DATASHET IDT70P3537 IDT70P3517

Part	Datasheet
IDT70P3517S233RM	IDT70P3517S233RM (pdf)

Related Parts	Information
IDT70P3537S250RM	IDT70P3537S250RM
IDT70P3517S250RM	IDT70P3517S250RM
IDT70P3517S233RMI	IDT70P3517S233RMI
IDT70P3537S233RM	IDT70P3537S233RM
IDT70P3537S233RMI	IDT70P3537S233RMI

PDF Datasheet Preview
512K/256K x36 SYNCHRONOUS DUAL QDR-IITM PRELIMINARY DATASHET IDT70P3537 IDT70P3517 18Mb Density 512K x 36 Also available 9Mb Density 256K x 36 QDR-II x 36 Burst-of-2 Interface Commercial 233MHz, 250MHz Two independent ports True Dual-Port Access to common memory Separate, Independent Read and Write Data Buses on each Port Supports concurrent transactions Two-Word Burst on all DPRAM accesses DDR Double Data Rate Multiplexed Address Bus One Read and One Write request per clock cycle DDR Double Data Rate Data Buses Four word burst data Two Read and Two Write per clock on each port Four word transfers each of Read & Write per clock cycle per port four word bursts on 2 ports Octal Data Rate Port Enable pins E0,E1 for depth expansion Dual Echo Clock Output with DLL-based phase alignment High Speed Transceiver Logic inputs scaled to receive signals from 1.4V to 1.9V Scalable output drivers Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V Output impedance adjustable from 35 ohms to 70 ohms 1.8V Core Voltage VDD 576-ball Flip Chip BGA 25mm x 25mm, 1.0mm ball pitch JTAG Interface - IEEE Compliant Functional Block Diagram EL[1:0] D0 L - D3 5 L KL A0L- A17L 2 RL WL BW 0L- BW 3L KL VREFL LEFT PORT DATA REGISTER AND LOGIC ZQL 1 Q0 L - Q3 5 L CQL, C Q L LEFT PORT ADDRESS REGISTER AND LOGIC VREFL OUTPUT BUFFER SELECT OUTPUT REGISTER WRITE REGISTER KL CL, C L KL, KL TDI TDO SENSE AMPS EP[1:0] WRITE DRIVER 512/256K x 36 MEMORY ARRAY SENSE AMPS ADDRESS DECODE JTAG TCK TMS TR S T VREFR OUTPUT REGISTER SELECT OUTPUT BUFFER Ordering Information Device Type Power Speed A Package A Process/ Temperature Range Preliminary Datasheet Commercial Temperatue Range Blank Commercial 0°C to +70°C RoHS Compliant Flip Chip BGA Commercial Only Com’l & Ind’l Speed in Megahertz Standard Power 70P3537 18Mbit 512K x 36 Dual QDR-IITM Static RAM 70P3517 9Mbit 256K x 36 Dual QDR-IITM Static RAM 5677 drw17 Preliminary Datasheet Description "PRELIMINARY" datasheets contain descriptions for products that are in early release. Datasheet Document History 7/11/2007 Initial release of Preliminary Datasheet 8/05/2008 Page 9 Corrected a typo in DC Chars table 01/19/09 Page 20 Removed "IDT" from orderable part number CORPORATE HEADQUARTERS for SALES: 6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 San Jose, CA 95138 fax 408-284-2775 The IDT logo is a registered trademark of Integrated Device Technology, Inc. for Tech Support 408-284-2794 January 29, 2009

PDF Datasheet Preview

512K/256K x36 SYNCHRONOUS DUAL QDR-IITM

PRELIMINARY DATASHET IDT70P3537 IDT70P3517
18Mb Density 512K x 36

Also available 9Mb Density 256K x 36 QDR-II x 36 Burst-of-2 Interface

Commercial 233MHz, 250MHz Two independent ports

True Dual-Port Access to common memory Separate, Independent Read and Write Data Buses on each

Port Supports concurrent transactions Two-Word Burst on all DPRAM accesses DDR Double Data Rate Multiplexed Address Bus

One Read and One Write request per clock cycle DDR Double Data Rate Data Buses

Four word burst data Two Read and Two Write per clock on
each port

Four word transfers each of Read & Write per clock cycle per
port four word bursts on 2 ports Octal Data Rate Port Enable pins E0,E1 for depth expansion Dual Echo Clock Output with DLL-based phase alignment High Speed Transceiver Logic inputs
scaled to receive signals from 1.4V to 1.9V Scalable output drivers

Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V

Output impedance adjustable from 35 ohms to 70 ohms 1.8V Core Voltage VDD 576-ball Flip Chip BGA 25mm x 25mm, 1.0mm ball pitch JTAG Interface - IEEE Compliant

Functional Block Diagram

EL[1:0]

D0 L - D3 5 L KL

A0L- A17L 2 RL WL

BW 0L- BW 3L KL

VREFL

LEFT PORT DATA

REGISTER AND LOGIC

ZQL 1 Q0 L - Q3 5 L CQL, C Q L

LEFT PORT ADDRESS REGISTER AND LOGIC

VREFL

OUTPUT BUFFER SELECT OUTPUT REGISTER

WRITE REGISTER

KL CL, C L

KL, KL

TDI TDO

SENSE AMPS

EP[1:0]

WRITE DRIVER
512/256K x 36 MEMORY ARRAY

SENSE AMPS

ADDRESS DECODE

JTAG

TCK TMS TR S T

VREFR

OUTPUT REGISTER SELECT OUTPUT BUFFER
Ordering Information

Device Type

Power Speed

A Package

A Process/ Temperature Range

Preliminary Datasheet Commercial Temperatue Range

Blank Commercial 0°C to +70°C

RoHS Compliant Flip Chip BGA

Commercial Only

Com’l & Ind’l

Speed in Megahertz

Standard Power
70P3537 18Mbit 512K x 36 Dual QDR-IITM Static RAM 70P3517 9Mbit 256K x 36 Dual QDR-IITM Static RAM
5677 drw17

Preliminary Datasheet Description
"PRELIMINARY" datasheets contain descriptions for products that are in early release.

Datasheet Document History
7/11/2007 Initial release of Preliminary Datasheet 8/05/2008 Page 9 Corrected a typo in DC Chars table 01/19/09 Page 20 Removed "IDT" from orderable part number

CORPORATE HEADQUARTERS
for SALES:
6024 Silver Creek Valley Road
800-345-7015 or 408-284-8200

San Jose, CA 95138
fax 408-284-2775

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
for Tech Support 408-284-2794

January 29, 2009

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT70P3517S233RM Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT70P3517S233RM 637318