MT45V256KW16PEGA-55 WT TR

MT45V256KW16PEGA-55 WT TR Datasheet

MT45V256KW16PEGA

Part	Datasheet
MT45V256KW16PEGA-55 WT TR	MT45V256KW16PEGA-55 WT TR (pdf)

Related Parts	Information
MT45V256KW16PEGA-70 WT TR	MT45V256KW16PEGA-70 WT TR

PDF Datasheet Preview
4Mb 3.0V Core Async/Page PSRAM Memory 256K x 16 Features 3.0V Core Async/Page PSRAM Memory MT45V256KW16PEGA • Asynchronous and page mode interface • Random access time 55ns and 70ns • VCC, VCCQ voltages VCC VCCQ • Page mode read access 16-word page size Interpage read access 55ns and 70ns Intrapage read access 15ns and 20ns • Low power consumption Asynchronous READ <30mA Intrapage READ <18mA Standby <140µA Deep power-down DPD <45µA TYP at 25°C • Low-power features Partial-array refresh PAR DPD mode Options • Configuration 256K x 16 • Package 48-ball VFBGA “green” • Access time 55ns 70ns • Operating temperature range Wireless to +85°C Industrial to +85°C Designator MT45V256KW16PE -55 -70 WT IT Figure 1 48-Ball VFBGA Ball Assignments LB# OE# A0 A2 ZZ# DQ8 UB# CE# DQ0 DQ9 DQ10 A5 DQ1 DQ2 D VssQ DQ11 A17 A7 DQ3 Vcc E VccQ DQ12 NC A16 DQ4 Vss F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 NC A12 A13 WE# DQ7 H DNU A8 A9 A10 A11 NC Top view Ball down Part Number Example: MT45V256KW16PEGA-55WT Micron Technology, Inc., reserves the right to change products or specifications without notice. 2007 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 4Mb 3.0V Core Async/Page PSRAM Memory 256K x 16 Table of Contents Table of Contents Features Options Designator Table of Contents List of Figures List of Tables. General Description Functional Block Diagram. Ball Descriptions Bus Operations Part Numbering Information Micron Technology, Inc., reserves the right to change products or specifications without notice. 2007 Micron Technology, Inc. All rights reserved. 4Mb 3.0V Core Async/Page PSRAM Memory 256K x 16 List of Figures List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24: 48-Ball VFBGA Ball Assignments. Functional Block Diagram 256K x 16 Part Number Chart Power-Up Initialization Timing. READ Operation WRITE Operation Page Mode READ Operation ADV = LOW . Software Access PAR Functionality. Configuration Register Bit Mapping. Load Configuration Register Operation Using ZZ#. Load Configuration Register Read Configuration Register Typical Refresh Current vs. Temperature AC Input/Output Reference Waveform Output Load Circuit Power-Up Initialization Period Load Configuration Register Deep Power-Down Entry and Exit Single READ Operation WE# = VIH . Page Mode READ Operation WE# = VIH WRITE Cycle WE# Control WRITE Cycle CE# Control WRITE Cycle LB#/UB# Control . 48-Ball VFBGA

PDF Datasheet Preview

4Mb 3.0V Core Async/Page PSRAM Memory 256K x 16 Features
3.0V Core Async/Page PSRAM Memory

MT45V256KW16PEGA
• Asynchronous and page mode interface
• Random access time 55ns and 70ns
• VCC, VCCQ voltages

VCC VCCQ
• Page mode read access 16-word page size Interpage read access 55ns and 70ns Intrapage read access 15ns and 20ns
• Low power consumption Asynchronous READ <30mA Intrapage READ <18mA Standby <140µA Deep power-down DPD <45µA TYP at 25°C
• Low-power features Partial-array refresh PAR DPD mode

Options
• Configuration 256K x 16
• Package 48-ball VFBGA “green”
• Access time 55ns 70ns
• Operating temperature range Wireless to +85°C Industrial to +85°C

Designator

MT45V256KW16PE
-55 -70

WT IT

Figure 1 48-Ball VFBGA Ball Assignments

LB# OE# A0

A2 ZZ#

DQ8 UB#

CE# DQ0

DQ9 DQ10 A5

DQ1 DQ2

D VssQ DQ11 A17 A7 DQ3 Vcc

E VccQ DQ12 NC A16 DQ4 Vss

F DQ14 DQ13 A14 A15 DQ5 DQ6

G DQ15 NC A12 A13 WE# DQ7

H DNU A8

A9 A10 A11 NC

Top view Ball down

Part Number Example:

MT45V256KW16PEGA-55WT

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2007 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
4Mb 3.0V Core Async/Page PSRAM Memory 256K x 16 Table of Contents

Table of Contents

Features Options Designator

Table of Contents List of Figures List of Tables. General Description Functional Block Diagram. Ball Descriptions Bus Operations Part Numbering Information

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2007 Micron Technology, Inc. All rights reserved.
4Mb 3.0V Core Async/Page PSRAM Memory 256K x 16 List of Figures

List of Figures

Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24:
48-Ball VFBGA Ball Assignments. Functional Block Diagram 256K x 16 Part Number Chart Power-Up Initialization Timing. READ Operation WRITE Operation Page Mode READ Operation ADV = LOW . Software Access PAR Functionality. Configuration Register Bit Mapping. Load Configuration Register Operation Using ZZ#. Load Configuration Register Read Configuration Register Typical Refresh Current vs. Temperature AC Input/Output Reference Waveform Output Load Circuit Power-Up Initialization Period Load Configuration Register Deep Power-Down Entry and Exit Single READ Operation WE# = VIH . Page Mode READ Operation WE# = VIH WRITE Cycle WE# Control WRITE Cycle CE# Control WRITE Cycle LB#/UB# Control . 48-Ball VFBGA

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT45V256KW16PEGA-55WTTR Datasheet file may be downloaded here without warranties.

Datasheet ID: MT45V256KW16PEGA-55WTTR 648396