MT18VDVF12872DY-335J1

MT18VDVF12872DY-335J1 Datasheet

MT18VDVF6472D 512MB MT18VDVF12872D 1GB

Part	Datasheet
MT18VDVF12872DY-335J1	MT18VDVF12872DY-335J1 (pdf)

PDF Datasheet Preview
512MB, 1GB x72, DR 184-Pin DDR VLP RDIMM Features DDR SDRAM VLP Registered DIMM MT18VDVF6472D 512MB MT18VDVF12872D 1GB For the latest data sheet, refer to Micron’s Web site: • 184-pin, very low profile dual in-line memory module VLP DIMM • Fast data transfer rates PC2100 or PC2700 • Utilizes 266 MT/s and 333 MT/s DDR SDRAM components • Registered inputs with one-clock delay • Phase-lock loop PLL clock driver to reduce loading • Supports ECC error detection and correction • 512MB 64 Meg x 72 and 1GB 128 Meg x 72 • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/ received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Auto refresh and self refresh modes • 7.8125µs maximum average periodic refresh interval • Serial presence detect SPD with EEPROM • Programmable READ CAS latency • Gold edge contacts • Dual rank Figure 1 184-Pin VLP DIMM MO-206 Very Low Profile Height 0.72in 18.29mm Options Marking • Package 184-pin DIMM standard 184-pin DIMM lead-free 1 • Memory clock, speed, CAS latency2 6ns 166MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = • PCB height Very Low-Profile 0.72in 18.29mm 1 -335 -2621 -26A1 -265 Notes:1. Contact Micron for product availability. CL = CAS READ latency registered mode adds one clock cycle to CL. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003, 2004, 2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512MB, 1GB x72, DR 184-Pin DDR VLP RDIMM Features Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 512MB 8K 4 BA0, BA1 256Mb 32 Meg x 8 1K 2 S0#, S1# 8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11 2 S0#, S1# Table 2 Part Numbers and Timing Parameters MT18VDVF6472DG-335__ MT18VDVF6472DY-335__ MT18VDVF6472DG-262__ MT18VDVF6472DY-262__ MT18VDVF6472DG-26A__ MT18VDVF6472DY-26A__ MT18VDVF6472DG-265__ MT18VDVF6472DY-265__ MT18VDVF6472DG-202__ MT18VDVF6472DY-202__ MT18VDVF12872DG-335__ MT18VDVF12872DY-335__ MT18VDVF12872DG-262__ MT18VDVF12872DY-262__ MT18VDVF12872DG-26A__ MT18VDVF12872DY-26A__ MT18VDVF12872DG-265__ MT18VDVF12872DY-265__ MT18VDVF12872DG-202__ MT18VDVF12872DY-202__ Note: Module Density 512MB Configuration 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 Module Bandwidth GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s Memory Clock/ Data Rate The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 5, "Burst Definition Table," on page Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003, 2004, 2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB x72, DR 184-Pin DDR VLP RDIMM Mode Register Definition Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 5, "CAS Latency Diagram," on page If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Figure 6, "CAS Latency Table," on page 13, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 4 Mode Register Definition Diagram BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 Reserved 2 4 8 Reserved M3 = 1 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 Reserved M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003, 2004, 2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB x72, DR 184-Pin DDR VLP RDIMM Mode Register Definition Table 5: Burst Definition Table Starting Column Burst Length Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved A1 A0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 A2 A1 A0

PDF Datasheet Preview

512MB, 1GB x72, DR 184-Pin DDR VLP RDIMM Features

DDR SDRAM VLP Registered DIMM

MT18VDVF6472D 512MB MT18VDVF12872D 1GB

For the latest data sheet, refer to Micron’s Web site:
• 184-pin, very low profile dual in-line memory module VLP DIMM
• Fast data transfer rates PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• Registered inputs with one-clock delay
• Phase-lock loop PLL clock driver to reduce loading
• Supports ECC error detection and correction
• 512MB 64 Meg x 72 and 1GB 128 Meg x 72
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/
received with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes
• 7.8125µs maximum average periodic refresh interval
• Serial presence detect SPD with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
• Dual rank

Figure 1 184-Pin VLP DIMM MO-206

Very Low Profile Height 0.72in 18.29mm

Options

Marking
• Package
184-pin DIMM standard 184-pin DIMM lead-free 1
• Memory clock, speed, CAS latency2
6ns 166MHz , 333 MT/s, CL =
7.5ns 133 MHz , 266 MT/s, CL = 2
7.5ns 133 MHz , 266 MT/s, CL = 2
7.5ns 133 MHz , 266 MT/s, CL =
• PCB height Very Low-Profile 0.72in 18.29mm 1
-335 -2621 -26A1 -265

Notes:1. Contact Micron for product availability. CL = CAS READ latency registered mode adds one clock cycle to CL.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003, 2004, 2005 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
512MB, 1GB x72, DR 184-Pin DDR VLP RDIMM Features

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
512MB
8K 4 BA0, BA1 256Mb 32 Meg x 8 1K 2 S0#, S1#
8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11 2 S0#, S1#

Table 2 Part Numbers and Timing Parameters

MT18VDVF6472DG-335__ MT18VDVF6472DY-335__ MT18VDVF6472DG-262__ MT18VDVF6472DY-262__ MT18VDVF6472DG-26A__ MT18VDVF6472DY-26A__ MT18VDVF6472DG-265__ MT18VDVF6472DY-265__ MT18VDVF6472DG-202__ MT18VDVF6472DY-202__ MT18VDVF12872DG-335__ MT18VDVF12872DY-335__ MT18VDVF12872DG-262__ MT18VDVF12872DY-262__ MT18VDVF12872DG-26A__ MT18VDVF12872DY-26A__ MT18VDVF12872DG-265__ MT18VDVF12872DY-265__ MT18VDVF12872DG-202__ MT18VDVF12872DY-202__

Note:

Module Density
512MB

Configuration
64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72

Module Bandwidth

GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s

Memory Clock/ Data Rate
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 5, "Burst Definition Table," on page

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB x72, DR 184-Pin DDR VLP RDIMM Mode Register Definition

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 5, "CAS Latency Diagram," on page

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Figure 6, "CAS Latency Table," on page 13, indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Figure 4 Mode Register Definition Diagram

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

Burst Length

M3 = 0 Reserved
2 4 8 Reserved

M3 = 1 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 Reserved

M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB x72, DR 184-Pin DDR VLP RDIMM Mode Register Definition

Table 5:

Burst Definition Table

Starting Column

Burst Length

Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved

A1 A0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2

A2 A1 A0

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT18VDVF12872DY-335J1 Datasheet file may be downloaded here without warranties.

Datasheet ID: MT18VDVF12872DY-335J1 648357