MT9HTF6472AY-800D1

MT9HTF6472AY-800D1 Datasheet

MT9HTF3272A 256MB MT9HTF6472A 512MB MT9HTF12872A 1GB

Part	Datasheet
MT9HTF6472AY-800D1	MT9HTF6472AY-800D1 (pdf)

Related Parts	Information
MT9HTF6472AY-53ED4	MT9HTF6472AY-53ED4
MT9HTF12872AY-53ED1	MT9HTF12872AY-53ED1
MT9HTF6472AY-667D4	MT9HTF6472AY-667D4
MT9HTF12872AY-40ED1	MT9HTF12872AY-40ED1
MT9HTF6472AY-40ED4	MT9HTF6472AY-40ED4

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256MB, 512MB, 1GB x72, SR, ECC 240-Pin DDR2 SDRAM UDIMM Features DDR2 SDRAM Unbuffered DIMM MT9HTF3272A 256MB MT9HTF6472A 512MB MT9HTF12872A 1GB For the latest data sheet, please refer to the Web site: • 240-pin, unbuffered dual in-line memory module UDIMM • Fast data transfer rates PC2-3200, PC2-4200, or PC2-5300 • 256MB 32 Meg x 72 , 512MB 64 Meg x 72 1GB 128 Meg x 72 • VDD = VDDQ = +1.8V • VDDSPD = +1.7V to +3.6V • JEDEC standard 1.8V I/O SSTL_18-compatible • Differential data strobe DQS, DQS# option • Four-bit prefetch architecture • DLL to align DQ and DQS transitions with CK • Multiple internal device banks for concurrent operation • Programmable CAS# latency CL • Posted CAS# additive latency AL • WRITE latency = READ latency - 1 tCK • Programmable burst lengths 4 or 8 • Adjustable data-output drive strength • 64ms, 8,192-cycle refresh • On-die termination ODT • Serial Presence Detect SPD with EEPROM • Gold edge contacts • Single rank Figure 1 240-Pin DIMM MO-237 R/C “A” Height 1.18in. 29.97mm Options • Package 240-pin DIMM lead-free • Frequency/CAS Latency1 3ns CL = 5 DDR2-667 2 3.75ns CL = 4 DDR2-533 5.0ns CL = 3 DDR2-400 • PCB Height 1.18in. 29.97mm Marking -667 -53E -40E Notes CL = CAS READ Latency. Not available in 1GB density. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003, 2004, 2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 256MB, 512MB, 1GB x72, SR, ECC 240-Pin DDR2 SDRAM UDIMM Features Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Page Size per Bank Device Configuration Column Addressing Module Rank Addressing 256MB 8K 4 BA0, BA1 1KB 256Mb 32 Meg x 8 1K 1 S0# 512MB 8K 16K 4 BA0, BA1 1KB 512Mb 64 Meg x 8 1K A0-A9 1 S0# 8K 16K 8 BA0, BA1, BA2 1KB 1Gb 128 Meg x 8 1K A0-A9 1 S0# Table 2 Key Timing Parameters Data Rate MT/s tRCD Speed Grade CL = 3 CL = 4 CL = 5 Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3 as shown in Figure 5, Mode Register MR Definition. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address as shown in Table 6, Burst Definition, on page DDR2 SDRAM devices support 4-bit burst and 8-bit burst modes only. For 8-bit burst mode, full interleave address ordering is supported however, sequential address ordering is nibble-based. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003, 2004, 2005 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB x72, SR, ECC 240-Pin DDR2 SDRAM UDIMM Mode Register MR Figure 5: Mode Register MR Definition 256MB Address Bus BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx MR PD WR DLL TM CAS# Latency BT Burst Length 512MB Address Bus BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx MR 0* PD WR DLL TM CAS# Latency BT Burst Length 1GB Address Bus BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* MR 0* PD WR DLL TM CAS# Latency BT Burst Length M12 PD mode M7 Mode 0 Normal 1 Test M2 M1 M0 Burst Length 0 Reserved 0 1 Reserved 0 Fast Exit Normal 1 Slow Exit Low Power M8 DLL Reset 0 No 1 Yes 0 10 0 11 1 00 1 01 4 8 Reserved 1 0 Reserved M11 M10 M9 WRITE RECOVERY 1 Reserved Reserved Burst Type Sequential Interleaved 1 01 1 10 1 11 6 Reserved M6 M5 M4 000 001 CAS Latency Reserved M15 M14 Mode Register Definition Mode Register MR 0 1 Extended Mode Register EMR 1 0 Extended Mode Register EMR2 1 Extended Mode Register EMR3 010 011 100 101 110 111 Reserved 3 4 Reserved

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256MB, 512MB, 1GB x72, SR, ECC 240-Pin DDR2 SDRAM UDIMM Features

DDR2 SDRAM Unbuffered DIMM

MT9HTF3272A 256MB MT9HTF6472A 512MB MT9HTF12872A 1GB

For the latest data sheet, please refer to the Web site:
• 240-pin, unbuffered dual in-line memory module UDIMM
• Fast data transfer rates PC2-3200, PC2-4200, or PC2-5300
• 256MB 32 Meg x 72 , 512MB 64 Meg x 72 1GB 128 Meg x 72
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC standard 1.8V I/O SSTL_18-compatible
• Differential data strobe DQS, DQS# option
• Four-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency CL
• Posted CAS# additive latency AL
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination ODT
• Serial Presence Detect SPD with EEPROM
• Gold edge contacts
• Single rank

Figure 1 240-Pin DIMM MO-237 R/C “A”

Height 1.18in. 29.97mm

Options
• Package 240-pin DIMM lead-free
• Frequency/CAS Latency1 3ns CL = 5 DDR2-667 2 3.75ns CL = 4 DDR2-533 5.0ns CL = 3 DDR2-400
• PCB Height 1.18in. 29.97mm

Marking
-667 -53E -40E

Notes CL = CAS READ Latency. Not available in 1GB density.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003, 2004, 2005 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
256MB, 512MB, 1GB x72, SR, ECC 240-Pin DDR2 SDRAM UDIMM Features

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Page Size per Bank Device Configuration Column Addressing Module Rank Addressing
256MB
8K 4 BA0, BA1
1KB 256Mb 32 Meg x 8
1K 1 S0#
512MB
8K 16K 4 BA0, BA1
1KB 512Mb 64 Meg x 8
1K A0-A9 1 S0#
8K 16K 8 BA0, BA1, BA2
1KB 1Gb 128 Meg x 8
1K A0-A9 1 S0#

Table 2 Key Timing Parameters

Data Rate MT/s
tRCD

Speed Grade

CL = 3

CL = 4

CL = 5
Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3 as shown in Figure 5, Mode Register MR Definition. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address as shown in Table 6, Burst Definition, on page DDR2 SDRAM devices support 4-bit burst and 8-bit burst modes only. For 8-bit burst mode, full interleave address ordering is supported however, sequential address ordering is nibble-based.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB x72, SR, ECC 240-Pin DDR2 SDRAM UDIMM Mode Register MR

Figure 5:

Mode Register MR Definition
256MB Address Bus

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx MR PD WR DLL TM CAS# Latency BT Burst Length
512MB Address Bus

BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx MR 0* PD WR DLL TM CAS# Latency BT Burst Length
1GB Address Bus

BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* MR 0* PD WR DLL TM CAS# Latency BT Burst Length

M12 PD mode

M7 Mode 0 Normal 1 Test

M2 M1 M0 Burst Length 0 Reserved 0 1 Reserved
0 Fast Exit Normal
1 Slow Exit Low Power

M8 DLL Reset 0 No 1 Yes
0 10 0 11 1 00 1 01
4 8 Reserved
1 0 Reserved

M11 M10 M9 WRITE RECOVERY
1 Reserved

Reserved

Burst Type

Sequential

Interleaved
1 01 1 10 1 11
6 Reserved

M6 M5 M4 000 001

CAS Latency Reserved

M15 M14 Mode Register Definition

Mode Register MR
0 1 Extended Mode Register EMR
1 0 Extended Mode Register EMR2
1 Extended Mode Register EMR3
010 011 100 101 110 111

Reserved 3 4

Reserved

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Datasheet ID: MT9HTF6472AY-800D1 648494