M2006-03-491.5200

M2006-03-491.5200 Datasheet

M2006-03

Part	Datasheet
M2006-03-491.5200	M2006-03-491.5200 (pdf)

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Integrated Circuit Systems, Inc. M2006-03 CMTS DIRECT CONVERSION ZERO IF CLOCK SOURCE The M2006-03 is a VCSO Voltage Controlled SAW Oscillator based clock generator PLL designed for frequency translation and jitter attenuation of a master reference clock in a cable modem termination system CMTS . External loop filter components allow tailoring of the PLL loop response. The M2006-03 includes a phase-slope limiting feature to prevent disruptive output clock phase changes upon input reference reselection. Integrated SAW surface acoustic wave delay line VCSO center frequency of 491.52MHz Jitter 9ps rms, typical, over 100Hz to 12kHz Jitter 3ps rms, typical, over 12kHz to 1GHz PLL phase slope limiter circuit Single-ended reference inputs support LVCMOS, LVTTL All output clocks are differential LVPECL compatible Two downstream clocks, frequency-selectable One upstream clock, frequency-selectable REF_OUT always provides a 10.24MHz reference clock All output rising edges aligned to within 1nsec of selected input reference rising edge unless M2_SEL= 1 Output duty cycle 47-53% worse case Single 3.3V power supply Small 9 x 9 mm SMT surface mount package PIN ASSIGNMENT 9 x 9 mm SMT US_CLK nUS_CLK DS_CLK_SEL REF_CLK1 REF_CLK0 REF_SEL VCCA VCC nREF_OUT REF_OUT M1_SEL M2_SEL VCC DNC 31 M 2 0 6 - 0 3 15 Top View US_CLK_SEL1 US_CLK_SEL0 nDS_CLK_1 DS_CLK_1 GND nDS_CLK_0 DS_CLK_0 VCC GND nOP_IN OP_OUT nOP_OUT OP_IN Figure 1 Pin Assignment Selectable Frequencies MHz for M2006-03-491.5200 Input Ref. Clock VCSO Frequency Downstream Clock: Upstream Clock Output Ref. Clock: or MHz or MHz or MHz Table 1 Selectable Frequencies MHz for M2006-03-491.5200 The M2006-03 is available with a 491.52MHz VCSO frequency that is specifically designed to support DOCSIS modem applications. As such, the M2006-03-491.520 see “Ordering Information” on pg. 6 accepts input reference frequencies of and 20.48MHz. Input Reference For the M2006-03-491.5200, which has a VCSO frequency of 491.52MHz, the four feedback divider values enable use with these corresponding input reference frequencies: M2006-03-491.5200 M2006-03-491.5200 VSCO Frequency MHz M Feedback Divider Value Input Reference Frequency MHz 120 48 Table 4 Feedback Divider Values and Input Reference Frequencies Because both inputs to the phase detector have the same frequency, the PLL can control the VCSO to keep it locked to the input reference clock. Post-PLL Dividers The M2006-03 also features three post-PLL dividers the downstream “DS” divider, the upstream “US” divider, and the output reference “REF” divider. The selectable reference inputs are applied to the REF_CLK1 and REF_CLK0 input pins as necessary. The REF_SEL pin selects the reference input: • REF_SEL = 1 selects REF_CLK1. • REF_SEL = 0 selects REF_CLK0. The selected reference clock is supplied directly to the phase detector of the PLL. The PLL The PLL Phase Locked Loop includes the phase detector, the VCSO, and two feedback dividers labeled “M1 Divider” and “M2 Divider” . The product of the two feedback divider values equals the overall feedback divider value “M”. M1 x M2 = M The M1_SEL and M2_SEL pins select the individual M1 and M2 divider values and, taken in combination, the overall feedback divider value “M” . M1 Overall Feedback M2_SEL M1_SEL Value x Value = Divider “M” Value Table 3 Combined Feedback Divider Selectors and Values “M” is used to divide the VCSO frequency so that it matches the input reference frequency. The relationship between the VCSO frequency, the M Divider, and the input reference frequency is: Fvcso ÷ M = Fref_in The DS Divider Divides the VCSO frequency to produce one of two downstream output frequencies 1/2 or 1/1 of the VCSO frequency . The DS_CLK_SEL pin determines the DS Divider value. DS_CLK_SEL M2006-03-491.5200 DS Value Downstream Output Frequencies MHz Table 5 Downstream Divider Selector, Values, and Frequencies The US Divider Divides the VCSO frequency to produce one of four upstream output frequencies 1/12, 1/6, 1/3 or 1/1 of the VCSO frequency . The US_CLK_SEL1 and US_CLK_SEL0 pins determine the US Divider value. US_CLK_SEL1 US_CLK_SEL0 US Value M2006-03-491.5200 Upstream Output Frequencies MHz Table 6 Upstream Divider Selectors, Values, and Frequencies The REF Divider Used along with the M1 divider value to ensure that the output system reference clock always equals the VCSO frequency divided by The M1_SEL pin determines the REF Divider value. REF M1_SEL Value M2006-03-491.5200 ORDERING INFORMATION For VCSO Frequency MHz Order Part Number M2006-03-491.5200 Table 13 Ordering Information Other frequencies available upon request. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems ICS assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M2006-03 Datasheet Rev 6 of 6 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

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Integrated Circuit Systems, Inc.

M2006-03

CMTS DIRECT CONVERSION ZERO IF CLOCK SOURCE

The M2006-03 is a VCSO Voltage Controlled SAW Oscillator based clock generator PLL designed for frequency translation and jitter attenuation of a master reference clock in a cable modem termination system CMTS . External loop filter components allow tailoring of the PLL loop response.

The M2006-03 includes a phase-slope limiting feature to prevent disruptive output clock phase changes upon input reference reselection.

Integrated SAW surface acoustic wave delay line

VCSO center frequency of 491.52MHz

Jitter 9ps rms, typical, over 100Hz to 12kHz Jitter 3ps rms, typical, over 12kHz to 1GHz

PLL phase slope limiter circuit

Single-ended reference inputs support LVCMOS, LVTTL

All output clocks are differential LVPECL compatible

Two downstream clocks, frequency-selectable

One upstream clock, frequency-selectable

REF_OUT always provides a 10.24MHz reference clock

All output rising edges aligned to within 1nsec of selected input reference rising edge unless M2_SEL= 1

Output duty cycle 47-53% worse case

Single 3.3V power supply

Small 9 x 9 mm SMT surface mount package

PIN ASSIGNMENT 9 x 9 mm SMT

US_CLK
nUS_CLK

DS_CLK_SEL

REF_CLK1

REF_CLK0

REF_SEL

VCCA

VCC nREF_OUT

REF_OUT M1_SEL M2_SEL VCC DNC
31 M 2 0 6 - 0 3 15

Top View

US_CLK_SEL1 US_CLK_SEL0 nDS_CLK_1 DS_CLK_1 GND nDS_CLK_0 DS_CLK_0 VCC GND
nOP_IN

OP_OUT
nOP_OUT

OP_IN

Figure 1 Pin Assignment

Selectable Frequencies MHz for M2006-03-491.5200

Input Ref. Clock VCSO Frequency Downstream Clock:

Upstream Clock Output Ref. Clock:
or MHz or MHz or MHz

Table 1 Selectable Frequencies MHz for M2006-03-491.5200
The M2006-03 is available with a 491.52MHz VCSO frequency that is specifically designed to support DOCSIS modem applications. As such, the M2006-03-491.520 see “Ordering Information” on pg. 6 accepts input reference frequencies of and 20.48MHz.

Input Reference

For the M2006-03-491.5200, which has a VCSO frequency of 491.52MHz, the four feedback divider values enable use with these corresponding input reference frequencies:

M2006-03-491.5200

M2006-03-491.5200

VSCO Frequency MHz

M Feedback Divider Value

Input Reference Frequency MHz
120 48

Table 4 Feedback Divider Values and Input Reference Frequencies

Because both inputs to the phase detector have the same frequency, the PLL can control the VCSO to keep it locked to the input reference clock.

Post-PLL Dividers

The M2006-03 also features three post-PLL dividers the downstream “DS” divider, the upstream “US” divider, and the output reference “REF” divider.

The selectable reference inputs are applied to the REF_CLK1 and REF_CLK0 input pins as necessary.

The REF_SEL pin selects the reference input:
• REF_SEL = 1 selects REF_CLK1.
• REF_SEL = 0 selects REF_CLK0.

The selected reference clock is supplied directly to the phase detector of the PLL.

The PLL

The PLL Phase Locked Loop includes the phase detector, the VCSO, and two feedback dividers labeled “M1 Divider” and “M2 Divider” .

The product of the two feedback divider values equals the overall feedback divider value “M”.

M1 x M2 = M

The M1_SEL and M2_SEL pins select the individual M1 and M2 divider values and, taken in combination, the overall feedback divider value “M” .

M1 Overall Feedback

M2_SEL M1_SEL Value x Value = Divider “M” Value

Table 3 Combined Feedback Divider Selectors and Values
“M” is used to divide the VCSO frequency so that it matches the input reference frequency. The relationship between the VCSO frequency, the M Divider, and the input reference frequency is:

Fvcso ÷ M = Fref_in

The DS Divider Divides the VCSO frequency to produce one of two downstream output frequencies 1/2 or 1/1 of the VCSO frequency . The DS_CLK_SEL pin determines the DS Divider value.

DS_CLK_SEL

M2006-03-491.5200

DS Value Downstream Output Frequencies MHz

Table 5 Downstream Divider Selector, Values, and Frequencies

The US Divider Divides the VCSO frequency to produce one of four upstream output frequencies 1/12, 1/6, 1/3 or 1/1 of the VCSO frequency . The US_CLK_SEL1 and US_CLK_SEL0 pins determine the US Divider value.

US_CLK_SEL1 US_CLK_SEL0 US Value

M2006-03-491.5200

Upstream Output

Frequencies MHz

Table 6 Upstream Divider Selectors, Values, and Frequencies

The REF Divider Used along with the M1 divider value to ensure that the output system reference clock always equals the VCSO frequency divided by The M1_SEL pin determines the REF Divider value.

REF M1_SEL Value

M2006-03-491.5200
ORDERING INFORMATION

For VCSO Frequency MHz

Order Part Number

M2006-03-491.5200
Table 13 Ordering Information

Other frequencies available upon request.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems ICS assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

M2006-03 Datasheet Rev
6 of 6

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M2006-03-491.5200 Datasheet file may be downloaded here without warranties.

Datasheet ID: M2006-03-491.5200 637417