M58LT128KST8ZA6F TR

M58LT128KST8ZA6F TR Datasheet

M58LT128KST M58LT128KSB

Part	Datasheet
M58LT128KST8ZA6F TR	M58LT128KST8ZA6F TR (pdf)

Related Parts	Information
M58LT128KSB7ZA6E	M58LT128KSB7ZA6E
M58LT128KST7ZA6E	M58LT128KST7ZA6E
M58LT128KST8ZA6E	M58LT128KST8ZA6E
M58LT128KSB7ZA6F TR	M58LT128KSB7ZA6F TR
M58LT128KSB8ZA6F TR	M58LT128KSB8ZA6F TR
M58LT128KSB8ZA6E	M58LT128KSB8ZA6E
M58LT128KST7ZA6F TR	M58LT128KST7ZA6F TR

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M58LT128KST M58LT128KSB 128 Mbit 8 Mb x16, multiple bank, multilevel interface, burst V supply, secure flash memories - Supply voltage VDD = V to V for Program, Erase and Read VDDQ = V to V for I/O buffers VPP = 9 V for fast program - Synchronous/Asynchronous Read Synchronous Burst Read mode 52 MHz Asynchronous Page Read mode Random access 85 ns, 70 ns - Synchronous Burst Read Suspend - Programming time µs typical word program time using Buffer Enhanced Factory Program command - Memory organization Multiple bank memory array 8-Mbit banks Parameter blocks top or bottom location - Dual operations program/erase in one bank while read in others No delay between Read and Write operations - Block protection All blocks protected at power-up Any combination of blocks can be protected with zero latency Absolute write protection with VPP = VSS - Security Software security features 64-bit unique device number 2112-bit user programmable OTP Cells - Common flash interface CFI - 100 000 program/erase cycles per block TBGA64 ZA 10 x 13 mm - Electronic signature Manufacturer code 20h Top device codes M58LT128KST 88D6h Bottom device codes M58LT128KSB 88D7h - TBGA64 package RoHS compliant available July 2010 1/110 Contents Contents M58LT128KST, M58LT128KSB Description 7 Signal descriptions 12 Address inputs A0-A22 12 Data inputs/outputs DQ0-DQ15 12 Chip Enable E 12 Output Enable G 12 Write Enable W 12 Reset RP 12 Latch Enable L 13 Clock K 13 Wait 13 VDD supply voltage 13 VDDQ supply voltage 13 VPP program supply voltage 13 VSS ground 14 VSSQ ground 14 Bus operations 15 Bus Read 15 Bus Write 15 Address Latch 15 Output Disable 15 Standby 16 Reset 16 Command interface 17 Read Array command 18 Read Status Register command 18 5/110 List of figures List of figures M58LT128KST, M58LT128KSB Figure Figure Logic diagram 9 TBGA64 package connections top view through package 10 Memory map 11 Protection Register memory map 31 X-latency and data output configuration example. 43 Wait configuration example 43 AC measurement I/O waveform 54 AC measurement load circuit 55 Asynchronous random access Read AC waveforms 58 Asynchronous Page Read AC waveforms 59 Synchronous Burst Read AC waveforms 61 Single Synchronous Read AC waveforms 62 Synchronous Burst Read Suspend AC waveforms 63 Clock input AC waveform 64 Write AC waveforms, Write Enable controlled 65 Write AC waveforms, Chip Enable controlled 67 Reset and power-up AC waveforms 69 TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, bottom view package outline. 70 Program flowchart and pseudo code 91 Blank Check flowchart and pseudo code 92 Buffer Program flowchart and pseudo code 93 Program Suspend & Resume flowchart and pseudo code 94 Block Erase flowchart and pseudo code. 95 Erase Suspend & Resume flowchart and pseudo code 96 Protect/Unprotect operation flowchart and pseudo code 97 Protection Register Program flowchart and pseudo code 98 Buffer Enhanced Factory Program flowchart and pseudo code 99 6/110 M58LT128KST, M58LT128KSB The M58LT128KST/B are 128 Mbit 8 Mbit x 16 non-volatile secure Flash memories. They may be erased electrically at block level and programmed in system on a word-by-word basis using a V to V VDD supply for the circuitry and a V to V VDDQ supply for the Input/Output pins. An optional 9 V VPP power supply is provided to accelerate factory programming. The devices feature an asymmetrical block architecture, with an array of 131 blocks, divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 7 main blocks of 64 Kwords. The multiple bank architecture allows dual operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory map is shown in Figure The parameter blocks are located at the top of the memory address space for the M58LT128KST, and at the bottom for the M58LT128KSB. Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There is a buffer-enhanced factory programming command available to accelerate programming. Program And Erase Commands Are Written To The command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports Synchronous Burst Read and Asynchronous Read from all blocks of the memory array at power-up the device is configured for Asynchronous Read. In Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to 52 MHz. The Synchronous Burst Read operation can be suspended and resumed. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. The M58LT128KST/B features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency, enabling instant code and data protection. They can be protected individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are protected at power- up. 7/110 M58LT128KST, M58LT128KSB The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 one-time-programmable OTP Protection Registers of 128 bits each. The first Protection Register is divided into two segments a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment OTP by the user. The user programmable segment can be permanently protected. Figure 4, shows the Protection Register memory map. The M58LT128KST/B also has a full set of software security features that are not described in this datasheet, but are documented in a dedicated application note. For further information, please contact Numonyx. The M58LT128KST/B are offered in a TBGA64, 10 x 13 mm, 1 mm pitch package. They are supplied with all the bits erased set to 8/110 M58LT128KST, M58LT128KSB Figure Logic diagram A0-A22 W E G RP L K VDD VDDQ VPP 16 DQ0-DQ15 WAIT VSS VSSQ AI12887 Table Signal names Signal name Function A0-A22 DQ0-DQ15 E G W RP K L WAIT VDD VDDQ VPP VSS VSSQ NC DU Address inputs Data input/outputs, command inputs Chip Enable Output Enable Write Enable Reset Clock Latch Enable Wait Supply voltage Supply voltage for input/output buffers Optional supply voltage for fast program & erase Ground input/output supply Not Connected Internally Do Not Use Direction Inputs I/O Input Output Input Input 9/110 M58LT128KST, M58LT128KSB Figure TBGA64 package connections top view through package WAIT DQ15 Table Ordering information scheme Example: M58LT128KST Device type Architecture L = multilevel, multiple bank, burst mode Operating voltage T = VDD = V to V, VDDQ = V to V Density 128 = 128 Mbit x16 Technology K = 65nm technology Security S = Secure Parameter location T = Top boot B = Bottom boot Speed 8 = 85ns 7 = 70ns Package ZA = TBGA64, 10 x 13 mm, 1 mm pitch Temperature range 6 = to 85°C Packing option E = RoHS compliant package, standard packing F = RoHS compliant package, tape & reel packing T = tape & reel packing Blank = standard packing 8 ZA 6 E Devices are shipped from the factory with the memory content bits erased to For a list of available options speed, package, etc. or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. 72/110 M58LT128KST, M58LT128KSB Appendix A Block address tables Block address tables Table Top boot block addresses, M58LT128KST Bank 1 Size Kword Parameter Bank Bank 1 Bank 2

PDF Datasheet Preview

M58LT128KST M58LT128KSB
128 Mbit 8 Mb x16, multiple bank, multilevel interface, burst V supply, secure flash memories
- Supply voltage VDD = V to V for Program, Erase and Read VDDQ = V to V for I/O buffers VPP = 9 V for fast program
- Synchronous/Asynchronous Read Synchronous Burst Read mode 52 MHz Asynchronous Page Read mode Random access 85 ns, 70 ns
- Synchronous Burst Read Suspend - Programming time
µs typical word program time using Buffer Enhanced Factory Program command
- Memory organization Multiple bank memory array 8-Mbit banks Parameter blocks top or bottom location
- Dual operations program/erase in one bank while read in others No delay between Read and Write operations
- Block protection All blocks protected at power-up Any combination of blocks can be protected with zero latency Absolute write protection with VPP = VSS
- Security Software security features 64-bit unique device number 2112-bit user programmable OTP Cells
- Common flash interface CFI - 100 000 program/erase cycles per block

TBGA64 ZA 10 x 13 mm
- Electronic signature Manufacturer code 20h Top device codes M58LT128KST 88D6h Bottom device codes M58LT128KSB 88D7h
- TBGA64 package RoHS compliant available

July 2010
1/110

Contents

Contents

M58LT128KST, M58LT128KSB

Description 7

Signal descriptions 12

Address inputs A0-A22 12

Data inputs/outputs DQ0-DQ15 12

Chip Enable E 12

Output Enable G 12

Write Enable W 12

Reset RP 12

Latch Enable L 13

Clock K 13

Wait 13

VDD supply voltage 13 VDDQ supply voltage 13 VPP program supply voltage 13 VSS ground 14 VSSQ ground 14

Bus operations 15

Bus Read 15

Bus Write 15

Address Latch 15

Output Disable 15

Standby 16

Reset 16

Command interface 17

Read Array command 18

Read Status Register command 18
5/110

List of figures

List of figures

M58LT128KST, M58LT128KSB

Figure

Figure

Logic diagram 9 TBGA64 package connections top view through package 10 Memory map 11 Protection Register memory map 31 X-latency and data output configuration example. 43 Wait configuration example 43 AC measurement I/O waveform 54 AC measurement load circuit 55 Asynchronous random access Read AC waveforms 58 Asynchronous Page Read AC waveforms 59 Synchronous Burst Read AC waveforms 61 Single Synchronous Read AC waveforms 62 Synchronous Burst Read Suspend AC waveforms 63 Clock input AC waveform 64 Write AC waveforms, Write Enable controlled 65 Write AC waveforms, Chip Enable controlled 67 Reset and power-up AC waveforms 69 TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, bottom view package outline. 70 Program flowchart and pseudo code 91 Blank Check flowchart and pseudo code 92 Buffer Program flowchart and pseudo code 93 Program Suspend & Resume flowchart and pseudo code 94 Block Erase flowchart and pseudo code. 95 Erase Suspend & Resume flowchart and pseudo code 96 Protect/Unprotect operation flowchart and pseudo code 97 Protection Register Program flowchart and pseudo code 98 Buffer Enhanced Factory Program flowchart and pseudo code 99
6/110

M58LT128KST, M58LT128KSB

The M58LT128KST/B are 128 Mbit 8 Mbit x 16 non-volatile secure Flash memories. They may be erased electrically at block level and programmed in system on a word-by-word basis using a V to V VDD supply for the circuitry and a V to V VDDQ supply for the Input/Output pins. An optional 9 V VPP power supply is provided to accelerate factory programming.

The devices feature an asymmetrical block architecture, with an array of 131 blocks, divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 7 main blocks of 64 Kwords.

The multiple bank architecture allows dual operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory map is shown in Figure The parameter blocks are located at the top of the memory address space for the M58LT128KST, and at the bottom for the M58LT128KSB.

Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There is a buffer-enhanced factory programming command available to accelerate programming.

Program And Erase Commands Are Written To The command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards.

The device supports Synchronous Burst Read and Asynchronous Read from all blocks of the memory array at power-up the device is configured for Asynchronous Read. In Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to 52 MHz. The Synchronous Burst Read operation can be suspended and resumed.

The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven.

The M58LT128KST/B features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency, enabling instant code and data protection. They can be protected individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are protected at power- up.
7/110

M58LT128KST, M58LT128KSB

The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 one-time-programmable OTP Protection Registers of 128 bits each. The first Protection Register is divided into two segments a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment OTP by the user. The user programmable segment can be permanently protected. Figure 4, shows the Protection Register memory map.

The M58LT128KST/B also has a full set of software security features that are not described in this datasheet, but are documented in a dedicated application note. For further information, please contact Numonyx.

The M58LT128KST/B are offered in a TBGA64, 10 x 13 mm, 1 mm pitch package. They are supplied with all the bits erased set to
8/110

M58LT128KST, M58LT128KSB

Figure Logic diagram

A0-A22 W E G RP L K

VDD VDDQ VPP 16 DQ0-DQ15

WAIT

VSS VSSQ

AI12887

Table Signal names Signal name

Function

A0-A22 DQ0-DQ15 E G W RP K L WAIT VDD VDDQ VPP VSS VSSQ NC DU

Address inputs Data input/outputs, command inputs Chip Enable Output Enable Write Enable Reset Clock Latch Enable Wait Supply voltage Supply voltage for input/output buffers Optional supply voltage for fast program & erase Ground input/output supply Not Connected Internally Do Not Use

Direction Inputs I/O Input Output Input

Input
9/110

M58LT128KST, M58LT128KSB

Figure TBGA64 package connections top view through package

WAIT

DQ15
Table Ordering information scheme

Example:

M58LT128KST

Device type

Architecture

L = multilevel, multiple bank, burst mode

Operating voltage

T = VDD = V to V, VDDQ = V to V Density
128 = 128 Mbit x16

Technology

K = 65nm technology

Security

S = Secure

Parameter location

T = Top boot

B = Bottom boot

Speed
8 = 85ns
7 = 70ns

Package

ZA = TBGA64, 10 x 13 mm, 1 mm pitch

Temperature range
6 = to 85°C

Packing option

E = RoHS compliant package, standard packing

F = RoHS compliant package, tape & reel packing

T = tape & reel packing

Blank = standard packing
8 ZA 6 E

Devices are shipped from the factory with the memory content bits erased to

For a list of available options speed, package, etc. or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you.
72/110

M58LT128KST, M58LT128KSB

Appendix A Block address tables

Block address tables

Table Top boot block addresses, M58LT128KST

Bank 1

Size Kword

Parameter Bank

Bank 1

Bank 2

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Datasheet ID: M58LT128KST8ZA6FTR 648300