M45PE16-VMP6TG TR

M45PE16-VMP6TG TR Datasheet

M45PE16

Part	Datasheet
M45PE16-VMP6TG TR	M45PE16-VMP6TG TR (pdf)

PDF Datasheet Preview
M45PE16 16-Mbit, page-erasable serial flash memory with byte alterability and a 75 MHz SPI bus interface • SPI bus compatible serial interface • 75 MHz clock rate maximum • 16-Mbit page-erasable flash memory • Page of 256 bytes Page write in 11 ms typical Page program in ms typical Page erase in 10 ms typical • Sector erase 512 Kbits • Hardware write protection of the bottom sector 64 Kbytes • Electronic signature JEDEC standard two-byte signature 4015h Unique ID code UID with 16 bytes read- only, available upon customer • to V single supply voltage • Deep power-down mode 1 µA typical • More than 100 000 write cycles • More than 20 years data retention • Packages VFQFPN8 MP 6 x 5 mm SO8W MW 208 mils body width May 2008 1/47 Contents Contents M45PE16 Description 6 Signal descriptions 8 Serial data output Q 8 Serial data input D 8 Serial Clock C 8 Chip Select S 8 Reset 8 Write Protect W 8 VCC supply voltage 9 VSS ground 9 SPI modes 10 Operating features 12 Sharing the overhead of modifying data 12 An easy way to modify data 12 A fast way to modify data 13 Polling during a write, program or erase cycle 13 Reset 13 Active power, standby power and deep power-down modes 13 Status register 14 Protection modes 14 Memory organization 15 Instructions 17 Write enable WREN 18 Write disable WRDI 19 Read identification RDID 20 Read status register RDSR 21 WIP bit 21 2/47 M45PE16 Ordering information 44 3/47 List of tables List of tables M45PE16 Table Table Table 4/47 M45PE16 List of figures List of figures Figure Figure Figure Logic diagram 6 MLP and SO8 connections 7 Bus master and memory devices on the SPI bus 10 SPI modes supported 11 Block diagram 16 Write enable WREN instruction sequence 18 Write disable WRDI instruction sequence 19 Read identification RDID instruction sequence and data-out sequence 20 Read status register RDSR instruction sequence and data-out sequence 21 Read data bytes READ instruction sequence and data-out sequence 22 Read data bytes at higher speed FAST_READ instruction sequence and data-out sequence 23 Page write PW instruction sequence 25 Page program PP instruction sequence 27 Page erase PE instruction sequence 28 Sector erase SE instruction sequence 29 Deep power-down DP instruction sequence 30 Release from deep power-down RDP instruction sequence 31 Power-up timing 33 AC test measurement I/O waveform. 35 Serial input timing 39 Write protect setup and hold timing 39 Output timing 39 Reset AC waveforms 40 VFQFPN8 MLP8 8-lead very thin fine pitch quad flat package no lead, 6 x 5 mm, package outline 41 SO8W - 8 lead plastic small outline, 208 mils body width, package outline 43 5/47 M45PE16 The M45PE16 is a 16-Mbit 2 Mbit x8 bit serial paged flash memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. The page write instruction consists of an integrated page erase cycle followed by a page program cycle. The memory is organized as 32 sectors, each containing 256 pages. Each page is 256-byte wide. Thus, the whole memory can be viewed as consisting of 8192 pages, or 2,097,152 bytes. The memory can be erased a page at a time, using the page erase instruction, or a sector at a time, using the sector erase instruction. Important note Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of Figure Logic diagram D C S W Reset Q M45PE16 Table Signal names Signal name Serial Clock Serial data input Serial data output Chip Select Write Protect Reset VCC VSS Reset Supply voltage Ground Function 6/47 AI06884 Direction Input Output Input M45PE16 Figure MLP and SO8 connections D C Reset S M45PE16 7 VSS 6 VCC AI06885C There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. See Package mechanical section for package dimensions, and how to identify pin-1. 7/47 Ordering information 12 Ordering information M45PE16 Table Ordering information scheme Example: M45PE16 V MP 6 T P Device type M45PE = page-erasable serial flash memory Device function 16 = 16 Mbits 2 Mbit x8 Operating voltage V = VCC = to V Package MP = VFQFPN8 MLP8 6 x 5 mm MW = SO8W 208 mils width Device grade 6 = industrial temperature range, to 85 °C. Device tested with standard test flow Option blank = standard packing T = tape and reel packing Plating technology P or G = RoHS compliant Note: For a list of available options speed, package, etc. or for further information on any aspect of this device, please contact your nearest Numonyx sales office. 44/47 M45PE16 Version Changes 30-Apr-2003 Initial release. 04-Jun-2003 Description corrected of entering hardware protected mode W must be driven, and cannot be left unconnected . VIO min extended to -0.6V, and tPW typ , tPP typ improved. tWHSL and 26-Nov-2003 tSHWL added. MLP8 and SO16 pages added, and LGA package removed. Table of contents, and Pb-free options added. 31-Mar-2004 Document promoted to product preview. 23-Jul-2004 SO connections illustration corrected. Wording clarified for device grade in ordering information table. An easy way to modify data, A fast way to modify data, Page write PW 04-Aug-2005 and Page program PP sections updated to explain optimal use of page write and page program instructions. Table 12 AC characteristics - 50 MHz operation updated. 15-Jun-2006 Document put in new template. tSHQZ end timing line modified in Figure 22 Output timing. Packages are compliant. VDFPN and SO16W packages removed. SO8W and VFQFPN8 packages added see Section 11: Package mechanical . Blank option removed below Plating technology in Table 18 Ordering information scheme. Document status promoted to preliminary data. 16-Oct-2006 50 MHz frequency added, 25 MHz frequency removed. Figure 3 Bus master and memory devices on the SPI bus modified, Note 1 modified, Note 2 added. Small text changes. ICC3 updated in Table 11 DC characteristics. Table 12 AC characteristics - 50 MHz operation updated. VIO max modified in Table 7 Absolute maximum ratings. fR, tPW, tPP, updated in Table 12 AC characteristics - 50 MHz operation. Section Reset modified and the signal can no longer be driven Low to protect the array at a critical time. Section VCC supply voltage and Section VSS ground added. Figure 3 Bus master and memory devices on the SPI bus modified and explanatory paragraph added. 09-Feb-2007 At power-up The write in progress WIP bit is reset. Note modified below Table 10 Capacitance. Table 14 Reset conditions and Table 15 Timings after a Reset Low pulse added. Small text changes. Packages specifications updated see Section 11 Package mechanical . 45/47 M45PE16 Version Changes 10-Dec-2007 Applied Numonyx branding. Document status promoted from preliminary data to datasheet. Removed ‘low voltage’ from the title. Updated the value for the maximum clock frequency from 50 to 75 MHz throughout the document. 15-May-2008 Added Table 13 AC characteristics - 75 MHz operation and text in Section 11 Package mechanical. Modified Table 11 DC characteristics, Figure 3 Bus master and memory devices on the SPI bus, Section 3 SPI modes, and Section Read identification RDID . 46/47 M45PE16 Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

PDF Datasheet Preview

M45PE16
16-Mbit, page-erasable serial flash memory with byte alterability and a 75 MHz SPI bus interface
• SPI bus compatible serial interface
• 75 MHz clock rate maximum
• 16-Mbit page-erasable flash memory
• Page of 256 bytes

Page write in 11 ms typical Page program in ms typical Page erase in 10 ms typical
• Sector erase 512 Kbits
• Hardware write protection of the bottom sector 64 Kbytes
• Electronic signature JEDEC standard two-byte signature
4015h Unique ID code UID with 16 bytes read-
only, available upon customer
• to V single supply voltage
• Deep power-down mode 1 µA typical
• More than 100 000 write cycles
• More than 20 years data retention
• Packages

VFQFPN8 MP 6 x 5 mm

SO8W MW 208 mils body width

May 2008
1/47

Contents

Contents

M45PE16

Description 6

Signal descriptions 8

Serial data output Q 8

Serial data input D 8

Serial Clock C 8

Chip Select S 8

Reset 8

Write Protect W 8

VCC supply voltage 9 VSS ground 9

SPI modes 10

Operating features 12

Sharing the overhead of modifying data 12

An easy way to modify data 12

A fast way to modify data 13

Polling during a write, program or erase cycle 13

Reset 13

Active power, standby power and deep power-down modes 13

Status register 14

Protection modes 14

Memory organization 15

Instructions 17

Write enable WREN 18

Write disable WRDI 19

Read identification RDID 20

Read status register RDSR 21

WIP bit 21
2/47

M45PE16
Ordering information 44
3/47

List of tables

List of tables

M45PE16

Table

Table

Table
4/47

M45PE16

List of figures

List of figures

Figure

Figure

Figure

Logic diagram 6 MLP and SO8 connections 7 Bus master and memory devices on the SPI bus 10 SPI modes supported 11 Block diagram 16 Write enable WREN instruction sequence 18 Write disable WRDI instruction sequence 19 Read identification RDID instruction sequence and data-out sequence 20 Read status register RDSR instruction sequence and data-out sequence 21 Read data bytes READ instruction sequence and data-out sequence 22 Read data bytes at higher speed FAST_READ instruction sequence and data-out sequence 23 Page write PW instruction sequence 25 Page program PP instruction sequence 27 Page erase PE instruction sequence 28 Sector erase SE instruction sequence 29 Deep power-down DP instruction sequence 30 Release from deep power-down RDP instruction sequence 31 Power-up timing 33 AC test measurement I/O waveform. 35 Serial input timing 39 Write protect setup and hold timing 39 Output timing 39 Reset AC waveforms 40 VFQFPN8 MLP8 8-lead very thin fine pitch quad flat package no lead, 6 x 5 mm, package outline 41 SO8W - 8 lead plastic small outline, 208 mils body width, package outline 43
5/47

M45PE16

The M45PE16 is a 16-Mbit 2 Mbit x8 bit serial paged flash memory accessed by a high speed SPI-compatible bus.

The memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. The page write instruction consists of an integrated page erase cycle followed by a page program cycle.

The memory is organized as 32 sectors, each containing 256 pages. Each page is 256-byte wide. Thus, the whole memory can be viewed as consisting of 8192 pages, or 2,097,152 bytes.

The memory can be erased a page at a time, using the page erase instruction, or a sector at a time, using the sector erase instruction.

Important note

Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of

Figure Logic diagram

D C S W Reset

Q M45PE16

Table Signal names

Signal name

Serial Clock

Serial data input

Serial data output

Chip Select

Write Protect

Reset VCC VSS

Reset Supply voltage Ground

Function
6/47

AI06884

Direction Input Output Input

M45PE16 Figure MLP and SO8 connections

D C Reset S

M45PE16
7 VSS
6 VCC

AI06885C

There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.

See Package mechanical section for package dimensions, and how to identify pin-1.
7/47
Ordering information
12 Ordering information

M45PE16
Table Ordering information scheme

Example:

M45PE16

V MP 6 T P

Device type M45PE = page-erasable serial flash memory

Device function 16 = 16 Mbits 2 Mbit x8

Operating voltage V = VCC = to V

Package MP = VFQFPN8 MLP8 6 x 5 mm MW = SO8W 208 mils width

Device grade
6 = industrial temperature range, to 85 °C. Device tested with standard test flow

Option blank = standard packing T = tape and reel packing

Plating technology P or G = RoHS compliant

Note:

For a list of available options speed, package, etc. or for further information on any aspect of this device, please contact your nearest Numonyx sales office.
44/47

M45PE16

Version

Changes
30-Apr-2003 Initial release.
04-Jun-2003

Description corrected of entering hardware protected mode W must be driven, and cannot be left unconnected .

VIO min extended to -0.6V, and tPW typ , tPP typ improved. tWHSL and 26-Nov-2003 tSHWL added. MLP8 and SO16 pages added, and LGA package
removed. Table of contents, and Pb-free options added.
31-Mar-2004 Document promoted to product preview.
23-Jul-2004
SO connections illustration corrected. Wording clarified for device grade in ordering information table.

An easy way to modify data, A fast way to modify data, Page write PW
04-Aug-2005
and Page program PP sections updated to explain optimal use of page write and page program instructions. Table 12 AC characteristics -
50 MHz operation updated.
15-Jun-2006

Document put in new template.
tSHQZ end timing line modified in Figure 22 Output timing.

Packages are compliant. VDFPN and SO16W packages
removed. SO8W and VFQFPN8 packages added see Section 11:

Package mechanical . Blank option removed below Plating technology in
Table 18 Ordering information scheme.

Document status promoted to preliminary data.
16-Oct-2006
50 MHz frequency added, 25 MHz frequency removed.

Figure 3 Bus master and memory devices on the SPI bus modified,

Note 1 modified, Note 2 added. Small text changes.

ICC3 updated in Table 11 DC characteristics.

Table 12 AC characteristics - 50 MHz operation updated.

VIO max modified in Table 7 Absolute maximum ratings.
fR, tPW, tPP, updated in Table 12 AC characteristics - 50 MHz operation.

Section Reset modified and the signal can no longer be driven Low to protect the array at a critical time. Section VCC supply voltage and Section VSS ground added.

Figure 3 Bus master and memory devices on the SPI bus modified and
explanatory paragraph added.
09-Feb-2007

At power-up The write in progress WIP bit is reset.

Note modified below Table 10 Capacitance.

Table 14 Reset conditions and Table 15 Timings after a Reset Low pulse added. Small text changes.

Packages specifications updated see Section 11 Package mechanical .
45/47

M45PE16

Version

Changes
10-Dec-2007

Applied Numonyx branding.

Document status promoted from preliminary data to datasheet.

Removed ‘low voltage’ from the title. Updated the value for the maximum
clock frequency from 50 to 75 MHz throughout the document.
15-May-2008

Added Table 13 AC characteristics - 75 MHz operation and text in Section 11 Package mechanical.

Modified Table 11 DC characteristics, Figure 3 Bus master and memory
devices on the SPI bus, Section 3 SPI modes, and Section Read
identification RDID .
46/47

M45PE16

Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M45PE16-VMP6TGTR Datasheet file may be downloaded here without warranties.

Datasheet ID: M45PE16-VMP6TGTR 648295