SY58052UMG

SY58052UMG Datasheet

SY58052U

Part	Datasheet
SY58052UMG	SY58052UMG (pdf)

Related Parts	Information
SY58052UMG TR	SY58052UMG TR
SY58052UMI TR	SY58052UMI TR
SY58052UMI	SY58052UMI

PDF Datasheet Preview
Micrel, Inc. ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT AND OUTPUT TERMINATION Precision Precision SY58052U s Resynchronizes data to a reference clock s Guaranteed AC performance over temperature and voltage • DC-to > 10.7Gbps data rate throughput • DC-to > 7GHz clock fMAX • < 190ps Any In-to-Out tpd • tr / tf < 60ps s Ultra low-jitter design • < 1psRMS random jitter • < 10psPP deterministic jitter • < 10psPP total jitter clock s Internal input termination s Unique input termination and VT pin accepts DCand AC-coupled inputs CML, PECL s Internal output source termination s 400mV CML output swing s Power supply 2.5V ±5% or 3.3V ±10% s to 85°C temperature range s Available in a 16-pin 3mm x 3mm package s Data communication systems s Serial OC-192, OC-192+FEC data-to-clock realignment s Parallel 10Gbps for OC768 s All SONET OC-3 OC-768 applications s All Fibre Channel applications s All GigE applications FUNCTIONAL BLOCK DIAGRAM Precision The SY58052U is an ultra-fast, precision, low jitter datato-clock resynchronizer with a guaranteed maximum data and clock throughput of 10.7Gbps or 7GHz, respectively. The SY58052U is an ideal solution for backplane retiming or retiming after the data passes through long trace lengths. Serial data comes into the data input, and the CML output is synchronous to the input reference clock’s rising edge. The SY58052U differential inputs include a unique, internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards, both AC- and DC-coupled, without external resistor-bias and termination networks. The result is a clean, stub-free, low-jitter interface solution. The differential CML output is optimized for environments with internal source termination and a 400mV output swing. The SY58052U operates from a 2.5V or 3.3V supply and is guaranteed over the full industrial temperature range to +85°C . The SY58052U is part of a Micrel’s Precision product family. All support documentation can be found on Micrel’s web site at DATA /DATA VTCLK /CLK DATA /DATA /Q CLK /CLK R Data from Backplane Uncertain timing Q Clock from Backplane /Q DATA IN /RESET CLK Q OUT Retimed AnyGate and Precision Edge are registered trademarks of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-082010 or 408 955-1690 SY58052U DATA Q CLK Retimed Data Micrel, Inc. Precision SY58052U PACKAGE/ORDERING INFORMATION VTCLK GND VCC CLK /CLK DATA /DATA 16 15 14 13 56 78 Q GND /Q VTDATA /RESET GND VCC 16-Pin MLF-16 Ordering Information 1 Part Number SY58052UMI SY58052UMITR 2 SY58052UMG 3 Package Type MLF-16 MLF-16 MLF-16 SY58052UMGTR 2, 3 MLF-16 Operating Range Industrial Industrial Package Marking 052U 052U with Pb-Free bar-line indicator 052U with Pb-Free bar-line indicator Lead Finish Sn-Pb Sn-Pb-Free NiPdAu Pb-Free NiPdAu Notes Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. Tape and Reel. Pb-Free package recommended for new designs. PIN DESCRIPTION Pin Number 1, 2 Pin Name CLK, /CLK DATA, /DATA VTData /RESET 7, 10, 11, 14, 15 Exposed Pad 8, 13 12, 9 Q, /Q VTCLK Pin Function Differential Input This input pair is the clock signal that re-times the data signal at DATA, /DATA. Each pin of this pair internally terminates to the VTCLK pin to Note that this input will default to an indeterminate state if left open. See “Input Interface Applications” section. Differential Input This input pair is the signal to be synchronized by the CLK, /CLK signal. Each pin of this pair internally terminates to the VTD pin to Note that this input will default to an indeterminate state if left open. See “Input Interface Applications” section. Input Termination Center-Tap Each of the two inputs, DATA, /DATA terminates to this pin. The VTData pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section. TTL/CMOS-Compatible Input The /RESET input asynchronously forces the Q output to a logic “0” state whenever it is active low. Possible state changes due to rising edges on CLK, /CLK are ignored until /RESET goes inactive high. Ground. Exposed pad must be connected to the same potential as the GND pin. Positive Power Supply. Bypass with low ESR capacitors. Differential Output This CML output pair is the output of the flip-flop. The Data input is transferred to the Q output at the rising edge of CLK falling edge of /CLK . See “Input Interface Applications” section. Input Termination Center-Tap Each of the two inputs, CLK, /CLK terminates to this pin. The VTCLK pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section. TRUTH TABLES DATA X 0 1 /DATA X 1 0

PDF Datasheet Preview

Micrel, Inc.

ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT AND OUTPUT TERMINATION

Precision

Precision

SY58052U
s Resynchronizes data to a reference clock s Guaranteed AC performance over temperature and
voltage
• DC-to > 10.7Gbps data rate throughput
• DC-to > 7GHz clock fMAX
• < 190ps Any In-to-Out tpd
• tr / tf < 60ps s Ultra low-jitter design
• < 1psRMS random jitter
• < 10psPP deterministic jitter
• < 10psPP total jitter clock s Internal input termination s Unique input termination and VT pin accepts DCand AC-coupled inputs CML, PECL s Internal output source termination s 400mV CML output swing s Power supply 2.5V ±5% or 3.3V ±10% s to 85°C temperature range s Available in a 16-pin 3mm x 3mm package
s Data communication systems s Serial OC-192, OC-192+FEC data-to-clock
realignment s Parallel 10Gbps for OC768 s All SONET OC-3 OC-768 applications s All Fibre Channel applications s All GigE applications

FUNCTIONAL BLOCK DIAGRAM

Precision

The SY58052U is an ultra-fast, precision, low jitter datato-clock resynchronizer with a guaranteed maximum data and clock throughput of 10.7Gbps or 7GHz, respectively. The SY58052U is an ideal solution for backplane retiming or retiming after the data passes through long trace lengths. Serial data comes into the data input, and the CML output is synchronous to the input reference clock’s rising edge.

The SY58052U differential inputs include a unique, internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards, both AC- and DC-coupled, without external resistor-bias and termination networks. The result is a clean, stub-free, low-jitter interface solution. The differential CML output is optimized for environments with internal source termination and a 400mV output swing.

The SY58052U operates from a 2.5V or 3.3V supply and is guaranteed over the full industrial temperature range to +85°C . The SY58052U is part of a Micrel’s Precision product family.

All support documentation can be found on Micrel’s web site at

DATA
/DATA

VTCLK
/CLK

DATA /DATA
/Q CLK
/CLK R

Data from Backplane Uncertain timing Q Clock from Backplane /Q

DATA IN
/RESET

CLK Q OUT Retimed

AnyGate and Precision Edge are registered trademarks of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

M9999-082010 or 408 955-1690

SY58052U DATA

Q CLK

Retimed Data

Micrel, Inc.

Precision SY58052U
PACKAGE/ORDERING INFORMATION

VTCLK GND VCC

CLK /CLK DATA /DATA
16 15 14 13
56 78

Q GND /Q

VTDATA /RESET

GND VCC
16-Pin MLF-16
Ordering Information 1

Part Number SY58052UMI SY58052UMITR 2 SY58052UMG 3

Package Type

MLF-16 MLF-16 MLF-16

SY58052UMGTR 2, 3 MLF-16

Operating Range

Industrial

Industrial

Package Marking
052U
052U with Pb-Free bar-line indicator
052U with Pb-Free bar-line indicator

Lead Finish

Sn-Pb

Sn-Pb-Free NiPdAu

Pb-Free NiPdAu

Notes Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. Tape and Reel. Pb-Free package recommended for new designs.

PIN DESCRIPTION

Pin Number 1, 2

Pin Name CLK, /CLK

DATA, /DATA

VTData
/RESET
7, 10, 11, 14, 15

Exposed Pad
8, 13
12, 9

Q, /Q

VTCLK

Pin Function

Differential Input This input pair is the clock signal that re-times the data signal at DATA, /DATA. Each pin of this pair internally terminates to the VTCLK pin to Note that this input will default to an indeterminate state if left open. See “Input Interface Applications” section.

Differential Input This input pair is the signal to be synchronized by the CLK, /CLK signal. Each pin of this pair internally terminates to the VTD pin to Note that this input will default to an indeterminate state if left open. See “Input Interface Applications” section.

Input Termination Center-Tap Each of the two inputs, DATA, /DATA terminates to this pin. The VTData pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section.

TTL/CMOS-Compatible Input The /RESET input asynchronously forces the Q output to a logic “0” state whenever it is active low. Possible state changes due to rising edges on CLK, /CLK are ignored until /RESET goes inactive high.

Ground. Exposed pad must be connected to the same potential as the GND pin.

Positive Power Supply. Bypass with low ESR capacitors.

Differential Output This CML output pair is the output of the flip-flop. The Data input is transferred to the Q output at the rising edge of CLK falling edge of /CLK . See “Input Interface Applications” section.

Input Termination Center-Tap Each of the two inputs, CLK, /CLK terminates to this pin. The VTCLK pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section.

TRUTH TABLES

DATA X 0 1
/DATA X 1 0

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Datasheet ID: SY58052UMG 647943