SY100S341FC

SY100S341FC Datasheet

SY100S341 FINAL

Part	Datasheet
SY100S341FC	SY100S341FC (pdf)

PDF Datasheet Preview
8-BIT SHIFT REGISTER SY100S341 FINAL s Max. shift frequency of 600MHz s Max. Clock to Q delay of 1200ps s IEE min. of s Industry standard 100K ECL levels s Extended supply voltage option: VEE = to s Voltage and temperature compensation for improved noise immunity s Internal input pull-down resistors s 70% faster than Fairchild 300K at lower power s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages P5 P6 P7 VEES D7 Q7 Q6 The SY100S341 offer eight D-type, edge-triggered flipflops with both individual inputs for parallel operation as well as serial inputs for bidirectional shifting, and are designed for use in high-performance ECL systems. Data is clocked into the flip-flops on the rising edge of the clock. The mode of operation is selected by two Select inputs S0, S1 which determine if the device performs a shift, hold or parallel entry function, as described in the Truth Table. The inputs on these devices have pull-down resistors. PIN CONFIGURATIONS PIN NAMES Label CP S0 S1 D0 D7 P0 P7 Q0 Q7 VEES VCCA Function Clock Pulse Input Select Inputs Serial Inputs Parallel Inputs Data Outputs VEE Substrate VCCO for ECL Outputs P4 CP VEE VEES S0 S1 P3 11 10 9 8 7 6 5 Top View PLCC J28-1 19 20 21 22 23 24 25 Q5 Q4 VCCA VCC Q3 Q2 P2 P1 P0 VEES D0 Q0 Q1 P3 S1 S0 VEE CP P4 24 23 22 21 20 19 18 P5 17 P6 P0 3 D0 4 Q0 5 Top View 16 P7 Flatpack F24-1 14 Q7 13 Q8 7 8 9 10 11 12 Q2 Q3 VCC VCCA Q4 Q5 Amendment /0 Issue Date July, 1999 Micrel BLOCK DIAGRAM SY100S341 P6 Q1 PARALLEL LOAD SHIFT LEFT RIGHT HOLD DECODE S0 S1 PRODUCT ORDERING CODE Ordering Code SY100S341FC SY100S341JC SY100S341JCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Micrel 24 LEAD CERPACK F24-1 SY100S341 Micrel 28 LEAD PLCC J28-1 SY100S341 MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA TEL + 1 408 980-9191 FAX + 1 408 914-7878 WEB This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. 2000 Micrel Incorporated 7

PDF Datasheet Preview

8-BIT SHIFT REGISTER

SY100S341 FINAL
s Max. shift frequency of 600MHz s Max. Clock to Q delay of 1200ps s IEE min. of s Industry standard 100K ECL levels s Extended supply voltage option:

VEE = to s Voltage and temperature compensation for improved
noise immunity s Internal input pull-down resistors s 70% faster than Fairchild 300K at lower power s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC
packages

P5 P6 P7 VEES D7 Q7 Q6

The SY100S341 offer eight D-type, edge-triggered flipflops with both individual inputs for parallel operation as well as serial inputs for bidirectional shifting, and are designed for use in high-performance ECL systems. Data is clocked into the flip-flops on the rising edge of the clock.

The mode of operation is selected by two Select inputs S0, S1 which determine if the device performs a shift, hold or parallel entry function, as described in the Truth Table. The inputs on these devices have pull-down resistors.

PIN CONFIGURATIONS

PIN NAMES

Label CP S0 S1 D0 D7 P0 P7 Q0 Q7 VEES VCCA

Function Clock Pulse Input Select Inputs Serial Inputs Parallel Inputs Data Outputs VEE Substrate VCCO for ECL Outputs

P4 CP VEE VEES S0 S1 P3
11 10 9 8 7 6 5

Top View

PLCC

J28-1
19 20 21 22 23 24 25

Q5 Q4 VCCA VCC Q3 Q2

P2 P1 P0 VEES D0 Q0 Q1 P3 S1 S0 VEE CP P4
24 23 22 21 20 19
18 P5
17 P6

P0 3 D0 4 Q0 5

Top View 16 P7

Flatpack F24-1
14 Q7
13 Q8
7 8 9 10 11 12

Q2 Q3 VCC VCCA Q4 Q5

Amendment /0

Issue Date July, 1999

Micrel

BLOCK DIAGRAM

SY100S341

P6 Q1

PARALLEL LOAD

SHIFT LEFT RIGHT HOLD

DECODE

S0 S1
PRODUCT ORDERING CODE
Ordering Code

SY100S341FC SY100S341JC SY100S341JCTR

Package Type F24-1 J28-1 J28-1

Operating Range

Commercial

Micrel
24 LEAD CERPACK F24-1

SY100S341

Micrel
28 LEAD PLCC J28-1

SY100S341

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA TEL + 1 408 980-9191 FAX + 1 408 914-7878 WEB

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. 2000 Micrel Incorporated 7

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SY100S341FC Datasheet file may be downloaded here without warranties.

Datasheet ID: SY100S341FC 647931