PEF 22508 E V1.1-G

PEF 22508 E V1.1-G Datasheet

Octal E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications PEF 22508 E, Version

Part	Datasheet
PEF 22508 E V1.1-G	PEF 22508 E V1.1-G (pdf)

Related Parts	Information
PEF 22508 E V1.1	PEF 22508 E V1.1

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OctalLIUTM Octal E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications PEF 22508 E, Version Wireline Communications Never stop thinking. The information in this document is subject to change without notice. Edition 2005-06-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. OctalLIUTM PEF 22508 E PEF 22508 E, Octal E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications Previous Version: Trademarks are registered trademarks of Infineon Technologies AG. 10BaseS , EasyPort , VDSLite are trademarks of Infineon Technologies AG. is a registered trademark of Microsoft Corporation, of Linus Torvalds, of Visio Corporation, and of Adobe Systems Incorporated. Data Sheet OctalLIUTM PEF 22508 E Table of Contents Preface 10 Introduction 11 Features 12 Logic Symbol 14 Typical Applications 15 Pin Descriptions 16 Pin Diagram PG-LBGA-256 top view 16 Pin Definitions and Functions 17 Pin Strapping 40 Functional Description 41 Hardware 41 Software 41 Functional Overview 41 Block Diagram 42 Functional Blocks 42 Asynchronous Micro Controller Interface Intel or Motorola mode 42 Mixed Byte/Word Access 43 Serial Micro Controller Interfaces 44 SCI Interface 44 SPI Interface 48 Interrupt Interface 49 Boundary Scan Interface 51 Master Clocking Unit 53 PLL Reset and Configuring 54 Line Coding and Framer Interface Modes 55 Receive Path 56 Receive Line Interface 57 Receive Line Coding 57 Receive Line Termination Analog Switch 57 Receive Line Monitoring Mode 58 Loss-of-Signal Detection 61 Receive Equalization Network 62 Receive Line Attenuation Indication 62 Receive Clock and Data Recovery 62 Receive Jitter Attenuator 62 Receive Jitter Attenuation Performance 65 Jitter Tolerance E1 66 Output Jitter 68 Dual Receive Elastic Buffer 68 Additional Receiver Functions 69 Error Monitoring and Alarm Handling 69 Automatic Modes 70 Error Counter 70 One-Second Timer 70 Transmit Path 71 Transmit Line Interface 71 Transmit Clock TCLK 72 Automatic Transmit Clock Switching 72 Transmit Jitter Attenuator 73 Dual Transmit Elastic Buffer 74 Programmable Pulse Shaper and Line Build-Out 74 QuadLIUTM Compatible Programming 75 Data Sheet OctalLIUTM PEF 22508 E Table of Contents Programming with TXP 16:1 Registers 76 Transmit Line Monitor 77 Framer Interface 78 Test Functions 79 Pseudo-Random Binary Sequence Generation and Monitor 79 In-Band Loop Generation, Detection and Loop Switching 80 Remote Loop 81 Local Loop 82 Payload Loop-Back 82 Alarm Simulation 83 Multi Function Ports 83 Register Description 85 Detailed Register Description 86 Control Registers 90 Status Registers 140 Package Outlines 161 Electrical Characteristics 162 AC Characteristics 166 Master Clock Timing 166 JTAG Boundary Scan Interface 167 Reset 168 Asynchronous Microprocessor Interface 168 Transmit Clock TCLK Frequency Selection See Chapter Note that frequencies are not in ascend ordering. 000B , MHz. 001B , MHz. 010B , MHz. 011B , MHz. 100B , MHz. 101B , Reserved. 110B , Reserved. 111B , Reserved. Data Sheet OctalLIUTM PEF 22508 E Register DescriptionClock Mode Register 1 Field Bits SCFX ATCS Clock Mode Register 1 Type rw Select Corner Frequency of DCO-X Only applicable if CMR2.EXFAX = See Chapter and Chapter 0B , Corner frequency of DCO-X is 2 Hz. 1B , Corner frequency of DCO-X is Hz. Automatic Transmit Clock Switching See Chapter If TCLK is lost, automatically switching to FCLKX can be performed. Note Kind of used transmit clock source is shown in status register XCLKS. 0B , Automatic clock switching is disabled. 1B , Automatic clock switching is enabled. CMR1 Clock Mode Register 1 Offset xx44H Reset Value 00H ';66 Field DCS DXJA Bits Type Description Disable Clock-Switching In Slave mode LIM0.MAS = the DCO-R is synchronized on the recovered route clock. In case of loss-of-signal LOS the DCO-R switches automatically to the clock sourced by port SYNC, see also Table 0B , Automatic switching from RCLK to SYNC is enabled 1B , Automatic switching from RCLK to SYNC is disabled Disable Internal Transmit Jitter Attenuation Setting this bit disables the transmit jitter attenuation. Reading the data out of the transmit elastic buffer and transmitting on XL1/2 XDOP/N/XOID is done with the clock provided on pin TCLK. In transmit elastic buffer bypass mode the transmit clock is taken from FCLKX, independent of this bit. Data Sheet OctalLIUTM PEF 22508 E Register DescriptionClock Mode Register 2 Field Bits DXSS Clock Mode Register 2 Type rw DCO-X Synchronization Clock Source 0B , The DCO-X circuitry synchronizes to the internal reference clock

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OctalLIUTM

Octal E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications PEF 22508 E, Version

Wireline Communications

Never stop thinking.

The information in this document is subject to change without notice.

Edition 2005-06-02

Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

OctalLIUTM PEF 22508 E

PEF 22508 E, Octal E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications

Previous Version:

Trademarks
are registered trademarks of Infineon Technologies AG. 10BaseS , EasyPort , VDSLite are trademarks of Infineon Technologies AG. is a registered trademark of Microsoft Corporation, of Linus Torvalds, of Visio Corporation, and of Adobe Systems

Incorporated.

Data Sheet

OctalLIUTM PEF 22508 E

Table of Contents

Preface 10

Introduction 11 Features 12 Logic Symbol 14 Typical Applications 15

Pin Descriptions 16 Pin Diagram PG-LBGA-256 top view 16 Pin Definitions and Functions 17 Pin Strapping 40

Functional Description 41 Hardware 41 Software 41 Functional Overview 41 Block Diagram 42 Functional Blocks 42

Asynchronous Micro Controller Interface Intel or Motorola mode 42 Mixed Byte/Word Access 43

Serial Micro Controller Interfaces 44 SCI Interface 44 SPI Interface 48

Interrupt Interface 49 Boundary Scan Interface 51 Master Clocking Unit 53

PLL Reset and Configuring 54 Line Coding and Framer Interface Modes 55 Receive Path 56

Receive Line Interface 57 Receive Line Coding 57 Receive Line Termination Analog Switch 57 Receive Line Monitoring Mode 58 Loss-of-Signal Detection 61 Receive Equalization Network 62 Receive Line Attenuation Indication 62 Receive Clock and Data Recovery 62 Receive Jitter Attenuator 62

Receive Jitter Attenuation Performance 65 Jitter Tolerance E1 66 Output Jitter 68 Dual Receive Elastic Buffer 68 Additional Receiver Functions 69 Error Monitoring and Alarm Handling 69 Automatic Modes 70 Error Counter 70 One-Second Timer 70 Transmit Path 71 Transmit Line Interface 71 Transmit Clock TCLK 72 Automatic Transmit Clock Switching 72 Transmit Jitter Attenuator 73 Dual Transmit Elastic Buffer 74 Programmable Pulse Shaper and Line Build-Out 74 QuadLIUTM Compatible Programming 75

Data Sheet

OctalLIUTM PEF 22508 E

Table of Contents

Programming with TXP 16:1 Registers 76 Transmit Line Monitor 77 Framer Interface 78 Test Functions 79 Pseudo-Random Binary Sequence Generation and Monitor 79 In-Band Loop Generation, Detection and Loop Switching 80 Remote Loop 81 Local Loop 82 Payload Loop-Back 82 Alarm Simulation 83 Multi Function Ports 83

Register Description 85 Detailed Register Description 86

Control Registers 90 Status Registers 140

Package Outlines 161

Electrical Characteristics 162 AC Characteristics 166

Master Clock Timing 166 JTAG Boundary Scan Interface 167 Reset 168 Asynchronous Microprocessor Interface 168
Transmit Clock TCLK Frequency Selection See Chapter Note that frequencies are not in ascend ordering. 000B , MHz. 001B , MHz. 010B , MHz. 011B , MHz. 100B , MHz. 101B , Reserved. 110B , Reserved. 111B , Reserved.

Data Sheet

OctalLIUTM PEF 22508 E

Register DescriptionClock Mode Register 1

Field

Bits

SCFX

ATCS

Clock Mode Register 1

Type rw

Select Corner Frequency of DCO-X Only applicable if CMR2.EXFAX = See Chapter and Chapter 0B , Corner frequency of DCO-X is 2 Hz. 1B , Corner frequency of DCO-X is Hz. Automatic Transmit Clock Switching See Chapter If TCLK is lost, automatically switching to FCLKX can be performed.

Note Kind of used transmit clock source is shown in status register XCLKS.
0B , Automatic clock switching is disabled. 1B , Automatic clock switching is enabled.

CMR1 Clock Mode Register 1

Offset xx44H

Reset Value 00H
';66

Field DCS

DXJA

Bits

Type Description

Disable Clock-Switching

In Slave mode LIM0.MAS = the DCO-R is synchronized on the
recovered route clock. In case of loss-of-signal LOS the DCO-R switches
automatically to the clock sourced by port SYNC, see also Table
0B , Automatic switching from RCLK to SYNC is enabled 1B , Automatic switching from RCLK to SYNC is disabled

Disable Internal Transmit Jitter Attenuation

Setting this bit disables the transmit jitter attenuation. Reading the data
out of the transmit elastic buffer and transmitting on XL1/2

XDOP/N/XOID is done with the clock provided on pin TCLK. In transmit
elastic buffer bypass mode the transmit clock is taken from FCLKX,
independent of this bit.

Data Sheet

OctalLIUTM PEF 22508 E

Register DescriptionClock Mode Register 2

Field

Bits

DXSS

Clock Mode Register 2

Type rw

DCO-X Synchronization Clock Source 0B , The DCO-X circuitry synchronizes to the internal reference clock

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PEF22508EV1.1-G Datasheet file may be downloaded here without warranties.

Datasheet ID: PEF22508EV1.1-G 638461