TSXPC860SRVZQU66D

TSXPC860SRVZQU66D Datasheet

Part	Datasheet
TSXPC860SRVZQU66D	TSXPC860SRVZQU66D (pdf)

PDF Datasheet Preview
• Single Issue Integer Core • Precise Exception Model • Extensive System Development Support On-chip Watchpoints and Breakpoints Program Flow Tracking On-chip Emulation Once Development Interface • High Performance Dhrystone 52 MIPS at 50 MHz, 3.3V, Watts Total Power • Low Power < 241 mW at 25 MHz, 2.4V Internal, 3.3V I/O-core, Caches, MMUs, I/O • MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus Monitor, and Real-time Clocks • Single Issue, 32-bit Version of the Embedded PowerPC Core Fully Compatible with Book 1 of the PowerPC Architecture Definition with 32 x 32-bit Fixed Point Registers Embedded PowerPC Performs Branch Folding, Branch Prediction with Conditional Prefetch, without Conditional Execution 4-Kbyte Data Cache and 4-Kbyte Instruction Cache, Each with an MMU Instruction and Data Caches are Two-way, Set Associative, Physical Address, 4 Word Line Burst, Least Recently Used LRU Replacement, Lockable On-line Granularity MMUs with 32 Entry TLB, Fully Associative Instruction and Data TLBs MMUs Support Multiple Page Sizes of 4 KB, 16 KB, 256 KB, 512 KB and 8 MB 16 Virtual Address Spaces and 8 Protection Groups Advanced On-chip Emulation Debug Mode • Up to 32-bit Data Bus Dynamic Bus Sizing for 8- and 16-bit • 32 Address Lines • Fully Static Design • VCC = +3.3V ± 5% • fmax = 66 MHz 80 MHz TBC • Military Temperature Range -55°C < TC < +125°C • PD = W Typical at 66 MHz The TSPC860 PowerPC QUad Integrated Communication Controller Power QUICC is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in communications and networking systems. The Power QUICC pronounced “quick” can be described as a PowerPC-based derivative of the TS68EN360 QUICC . The CPU on the TSPC860 is a 32-bit PowerPC implementation that incorporates memory management units MMUs and instruction and data caches. The communications processor module CPM of the TS68EN360 QUICC has been enhanced with the addition of a Two-wire Interface TWI compatible with protocols such as I2C. Moderate to high digital signal processing DSP functionality has been added to the CPM. The memory controller has been enhanced, enabling the TSPC860 to support any type of memory, including high performance memories and newer dynamic random access memories DRAMs . Overall system functionality is completed with the addition of a PCMCIA socket controller supporting up to two sockets and a real-time clock. PBGA 357 ZP suffix 32-bit Quad Integrated Power QUICC Communication Controller TSPC860 Screening/Quality This product will be manufactured in full compliance with • According to Atmel Standards The TSPC860 is functionally composed of three major blocks • A 32-bit PowerPC Core with MMUs and Caches • A System Interface Unit • A Communications Processor Module Figure Block Diagram View of the TSPC860 Embedded PowerPC Core 4 or 16 KB I-Cache Instruction Bus I-MMU Load/store BUS 4 or 8 KB D-Cache D-MMU Unified Bus SYSTEM INTERFACE UNIT Memory Controller Bus Interface Unit System Functions Real Time Clock PCMCIA Interface Parallel I/O Baud Rate Generators Parallel Interface Port Interrupt Dual-Port Timers Controller 32-bit RISC µController and Program ROM Timer 16 Serial DMA and Virtual IDMA SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI TWI Time Slot Assigner Serial Interface 2 TSPC860 Main Features TSPC860 The Following is a List of the TSPC860’s Important Features • Fully Static Design • Four Major Power Saving Modes • 357 OMPAC Ball Grid Array Packaging Plastic • 32-bit Address and Data Busses • Flexible Memory Management • 4-Kbyte Physical Address, Two-way, Set-associative Data Cache • 4-Kbyte Physical Address, Two-way, Set-associative Instruction Cache • Eight-bank Memory Controller Glueless Interface to SRAM, DRAM, EPROM, FLASH and Other Peripherals Byte Write Enables and Selectable Parity Generation 32-bit Address Decodes With Bit Masks • System Interface Unit Clock Synthesizer Power Management Reset Controller PowerPC Decrementer And Time Base Real-time Clock Register Periodic Interrupt Timer Hardware Bus Monitor and Software Watchdog Timer IEEE JTAG Test Access Port • Communications Processor Module Embedded 32-bit RISC Controller Architecture for Flexible I/O Interfaces to PowerPC Core Through On-chip Dual-port Ram And Virtual Ordering Information TS X PC860 SR M ZP U 66 D Prefix Prototype Type Version MH, SR Temperature range TC M -55, +125°C V -40, +110°C Package ZP PBGA Max internal processor speed 2 40 MHz 50 MHz 66 MHz SR only 80 MHz SR only TBC Screening level 1 U Upscreening 1 For availability of the different versions, contact your sales office. Definitions Datasheet Status Validity Objective Specification This datasheet contains target and goal specification for discussion with customer and application validation. Before design phase. Target Specification This datasheet contains target or goal specification for product development. Valid during the design phase. Preliminary Specification ∝ site This datasheet contains preliminary data. Additional data may Valid before characterization be published later could include simulation result. phase. Preliminary Specification site This datasheet also contains characterization results. Valid before the industrialization phase. Product Specification This datasheet contains final product specification. Valid for production purpose. Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System IEC Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 88 TSPC860 Life Support Applications TSPC860 These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1 408 441-0311 FAX 1 408 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL 41 26-426-5555 FAX 41 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721-9778 FAX 852 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL 81 3-3523-3551 FAX 81 3-3523-7581

PDF Datasheet Preview

• Single Issue Integer Core
• Precise Exception Model
• Extensive System Development Support

On-chip Watchpoints and Breakpoints Program Flow Tracking On-chip Emulation Once Development Interface
• High Performance Dhrystone 52 MIPS at 50 MHz, 3.3V, Watts Total Power
• Low Power < 241 mW at 25 MHz, 2.4V Internal, 3.3V I/O-core, Caches, MMUs, I/O
• MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus Monitor, and Real-time Clocks
• Single Issue, 32-bit Version of the Embedded PowerPC Core Fully Compatible with Book 1 of the PowerPC Architecture Definition with 32 x 32-bit Fixed Point Registers Embedded PowerPC Performs Branch Folding, Branch Prediction with

Conditional Prefetch, without Conditional Execution 4-Kbyte Data Cache and 4-Kbyte Instruction Cache, Each with an MMU Instruction and Data Caches are Two-way, Set Associative, Physical Address,
4 Word Line Burst, Least Recently Used LRU Replacement, Lockable On-line Granularity MMUs with 32 Entry TLB, Fully Associative Instruction and Data TLBs MMUs Support Multiple Page Sizes of 4 KB, 16 KB, 256 KB, 512 KB and 8 MB 16 Virtual Address Spaces and 8 Protection Groups Advanced On-chip Emulation Debug Mode
• Up to 32-bit Data Bus Dynamic Bus Sizing for 8- and 16-bit
• 32 Address Lines
• Fully Static Design
• VCC = +3.3V ± 5%
• fmax = 66 MHz 80 MHz TBC
• Military Temperature Range -55°C < TC < +125°C
• PD = W Typical at 66 MHz

The TSPC860 PowerPC QUad Integrated Communication Controller Power QUICC is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in communications and networking systems. The Power QUICC pronounced “quick” can be described as a PowerPC-based derivative of the TS68EN360 QUICC .

The CPU on the TSPC860 is a 32-bit PowerPC implementation that incorporates memory management units MMUs and instruction and data caches. The communications processor module CPM of the TS68EN360 QUICC has been enhanced with the addition of a Two-wire Interface TWI compatible with protocols such as I2C. Moderate to high digital signal processing DSP functionality has been added to the CPM. The memory controller has been enhanced, enabling the TSPC860 to support any type of memory, including high performance memories and newer dynamic random access memories DRAMs . Overall system functionality is completed with the addition of a PCMCIA socket controller supporting up to two sockets and a real-time clock.

PBGA 357 ZP suffix
32-bit Quad Integrated Power QUICC Communication Controller

TSPC860

Screening/Quality

This product will be manufactured in full compliance with
• According to Atmel Standards

The TSPC860 is functionally composed of three major blocks
• A 32-bit PowerPC Core with MMUs and Caches
• A System Interface Unit
• A Communications Processor Module

Figure Block Diagram View of the TSPC860

Embedded PowerPC

Core
4 or 16 KB I-Cache

Instruction Bus

I-MMU

Load/store BUS
4 or 8 KB D-Cache

D-MMU

Unified Bus

SYSTEM INTERFACE UNIT

Memory Controller Bus Interface Unit System Functions Real Time Clock PCMCIA Interface

Parallel I/O

Baud Rate Generators

Parallel Interface Port

Interrupt Dual-Port

Timers Controller
32-bit RISC µController and Program ROM

Timer
16 Serial DMA and

Virtual IDMA

SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI TWI

Time Slot Assigner

Serial Interface
2 TSPC860

Main Features

TSPC860

The Following is a List of the TSPC860’s Important Features
• Fully Static Design
• Four Major Power Saving Modes
• 357 OMPAC Ball Grid Array Packaging Plastic
• 32-bit Address and Data Busses
• Flexible Memory Management
• 4-Kbyte Physical Address, Two-way, Set-associative Data Cache
• 4-Kbyte Physical Address, Two-way, Set-associative Instruction Cache
• Eight-bank Memory Controller

Glueless Interface to SRAM, DRAM, EPROM, FLASH and Other Peripherals Byte Write Enables and Selectable Parity Generation 32-bit Address Decodes With Bit Masks
• System Interface Unit Clock Synthesizer Power Management Reset Controller PowerPC Decrementer And Time Base Real-time Clock Register Periodic Interrupt Timer Hardware Bus Monitor and Software Watchdog Timer IEEE JTAG Test Access Port
• Communications Processor Module Embedded 32-bit RISC Controller Architecture for Flexible I/O Interfaces to PowerPC Core Through On-chip Dual-port Ram And Virtual
Ordering Information

TS X PC860 SR M ZP U 66 D

Prefix Prototype Type

Version MH, SR Temperature range TC

M -55, +125°C V -40, +110°C

Package ZP PBGA

Max internal processor speed 2 40 MHz 50 MHz 66 MHz SR only 80 MHz SR only TBC

Screening level 1 U Upscreening
1 For availability of the different versions, contact your sales office.

Definitions

Datasheet Status

Validity

Objective Specification

This datasheet contains target and goal specification for discussion with customer and application validation.

Before design phase.

Target Specification

This datasheet contains target or goal specification for product development.

Valid during the design phase.

Preliminary Specification ∝ site

This datasheet contains preliminary data. Additional data may Valid before characterization
be published later could include simulation result.
phase.

Preliminary Specification site

This datasheet also contains characterization results.

Valid before the industrialization phase.

Product Specification

This datasheet contains final product specification.

Valid for production purpose.

Limiting Values

Limiting values given are in accordance with the Absolute Maximum Rating System IEC Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.
88 TSPC860

Life Support Applications

TSPC860

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale.

Atmel Headquarters

Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1 408 441-0311 FAX 1 408 487-2600

Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL 41 26-426-5555 FAX 41 26-426-5500

Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721-9778 FAX 852 2722-1369

Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL 81 3-3523-3551 FAX 81 3-3523-7581

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Datasheet ID: TSXPC860SRVZQU66D 519447