ATR0621P-7FQY

ATR0621P-7FQY Datasheet

GPS Baseband Processor ATR0621P1 Automotive Summary

Part	Datasheet
ATR0621P-7FQY	ATR0621P-7FQY (pdf)

PDF Datasheet Preview
• 16 Channel GPS Correlator 8192 Search Bins with GPS Acquisition Accelerator Accuracy 2.5m CEP Stand-Alone, S/A off Time to First Fix 34s Cold Start Acquisition Sensitivity dBm Tracking Sensitivity dBm • Utilizes the Processor Core High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set EmbeddedICE In-circuit Emulator • 128 Kbyte Internal RAM • 384 Kbyte Internal ROM, Firmware Version V5.0 • Position Technology Provided by u-blox • Fully Programmable External Bus Interface EBI Maximum External Address Space of 8 Mbytes Up to 4 Chip Selects Software Programmable 8-bit/16-bit External Data Bus • 6-channel Peripheral Data Controller PDC • 8-level Priority, Individually Maskable, Vectored Interrupt Controller 2 External Interrupts • 32 User-programmable I/O Lines • 1 USB Device Port Universal Serial Bus USB V2.0 Full-speed Device Embedded USB V2.0 Full-speed Transceiver Suspend/Resume Logic Ping-pong Mode for Isochronous and Bulk Endpoints • 2 USARTs 2 Dedicated Peripheral Data Controller PDC Channels per USART • Master/Slave SPI Interface 2 Dedicated Peripheral Data Controller PDC Channels 8-bit to 16-bit Programmable Data Length 4 External Slave Chip Selects • Programmable Watchdog Timer • Advanced Power Management Controller APMC Peripherals Can Be Deactivated Individually Geared Master Clock to Reduce Power Consumption Sleep State with Disabled Master Clock Hibernate State with kHz Master Clock • Real Time Clock RTC • 2.3V to 3.6V or 1.8V Core Supply Voltage • Includes Power Supervisor • 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance • 4 Kbytes Battery Backup Memory • 9 mm x 9 mm 100-pin BGA Package LFBGA100 • RoHS-compliant GPS Baseband Processor ATR0621P1 Automotive Summary NOTE This is a summary document. The complete document is available. For more information, please contact your local Atmel sales office. The GPS baseband processor ATR0621P1 includes a 16-channel GPS correlator and is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The ATR0621P1 has two USART and an USB device port. This port is compliant with the Universal Serial Bus USB V2.0 full-speed device specification. The ATR0621P1 has a direct connection to off-chip memory, including Flash, through the External Bus Interface EBI . The ATR0621P1 includes full GPS firmware, licensed from u-blox AG, which performs the basic GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT Position/Velocity/Time applications, there is no need for off-chip Flash memory or ROM. The firmware supports e.g. the protocol and a binary protocol for PVT data, configuration and debugging, the RTCM protocol for DGPS, SBAS WAAS, EGNOS and MSAS and A-GPS aiding . It is also possible to store the configuration settings in an optional external EEPROM. The ATR0621P1 is manufactured using the high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator and a wide range of peripheral functions on a monolithic chip, the ATR0621P1 provides a highly-flexible and cost-effective solution for GPS applications. 2 ATR0621P1 Figure Block Diagram NSHDN NSLEEP XT_IN XT_OUT RF_ON CLK23 P15/ANTON P0/NANTSHORT P14/NAADET1 P25/NAADET0 P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 P9/EXTINT0 P2/BOOT_MODE P30/AGCOUT0 P8/STATUSLED P16/NEEPROM P11/EM_A21 P28/EM_A20 P10/EM_A0/NLB P7/NUB/NWR1 P6/NOE/NRD P5/NWE/NWR0 P4/nCS0 P3/nCS1 EM_A19 EM_A1 EM_DA15 EM_DA0 DBG_EN NTRST TDI TDO TCK TMS NRESET PIO2 Reset Controller JTAG Embedded ICE ARM7TDMI Interface to Off-Chip Memory EBI Watchdog Advanced Interrupt Controller Special Function PIO2 Controller SMD Generator Advanced Power Management Controller RTC SRAM Power Supply Manager Ordering Information Extended Type Number Package ATR0621P1-7FQY LFBGA100 ATR0621P1-7FHW ATR0622-EK1 ATR0622-DK1 LFBGA100 Package LFBGA100 Package R-LFBGA 100_G Dimensions in mm A1 Corner Top View 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K MPQ 2000 2000 1 Remarks 9 mm x 9 mm, mm pitch, ROM5, RoHS-compliant, automotive type 9 mm x 9 mm, mm pitch, ROM5, RoHS-compliant, green, automotive type Evaluation kit/road test kit Development kit including example design information 100x Bottom View A1 Corner 10 9 8 7 6 5 4 3 2 1 technical drawings according to DIN specifications A 4x C ref. Drawing-No. Issue 2; Seating plane C Moisture sensitivity level MSL = 3 12 ATR0621P1 ATR0621P1 History 4975BS-GPS-05/08 • Table 3-1 “ATR0621P1 Pinout” on page 5 Pin type of pin CLK23 changed. Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721-9778 Fax 852 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11

PDF Datasheet Preview

• 16 Channel GPS Correlator 8192 Search Bins with GPS Acquisition Accelerator Accuracy 2.5m CEP Stand-Alone, S/A off Time to First Fix 34s Cold Start Acquisition Sensitivity dBm Tracking Sensitivity dBm
• Utilizes the Processor Core High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set EmbeddedICE In-circuit Emulator
• 128 Kbyte Internal RAM
• 384 Kbyte Internal ROM, Firmware Version V5.0
• Position Technology Provided by u-blox
• Fully Programmable External Bus Interface EBI

Maximum External Address Space of 8 Mbytes Up to 4 Chip Selects Software Programmable 8-bit/16-bit External Data Bus
• 6-channel Peripheral Data Controller PDC
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller 2 External Interrupts
• 32 User-programmable I/O Lines
• 1 USB Device Port Universal Serial Bus USB V2.0 Full-speed Device Embedded USB V2.0 Full-speed Transceiver Suspend/Resume Logic Ping-pong Mode for Isochronous and Bulk Endpoints
• 2 USARTs 2 Dedicated Peripheral Data Controller PDC Channels per USART
• Master/Slave SPI Interface 2 Dedicated Peripheral Data Controller PDC Channels 8-bit to 16-bit Programmable Data Length 4 External Slave Chip Selects
• Programmable Watchdog Timer
• Advanced Power Management Controller APMC Peripherals Can Be Deactivated Individually Geared Master Clock to Reduce Power Consumption Sleep State with Disabled Master Clock Hibernate State with kHz Master Clock
• Real Time Clock RTC
• 2.3V to 3.6V or 1.8V Core Supply Voltage
• Includes Power Supervisor
• 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance
• 4 Kbytes Battery Backup Memory
• 9 mm x 9 mm 100-pin BGA Package LFBGA100
• RoHS-compliant

GPS Baseband Processor ATR0621P1 Automotive Summary

NOTE This is a summary document. The complete document is available. For more information, please contact your local Atmel sales office.

The GPS baseband processor ATR0621P1 includes a 16-channel GPS correlator and is based on the ARM7TDMI processor core.

This processor has a high-performance 32-bit RISC architecture and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The ATR0621P1 has two USART and an USB device port. This port is compliant with the Universal Serial Bus USB V2.0 full-speed device specification. The ATR0621P1 has a direct connection to off-chip memory, including Flash, through the External Bus Interface EBI .

The ATR0621P1 includes full GPS firmware, licensed from u-blox AG, which performs the basic GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT Position/Velocity/Time applications, there is no need for off-chip Flash memory or ROM. The firmware supports e.g. the protocol and a binary protocol for PVT data, configuration and debugging, the RTCM protocol for DGPS, SBAS WAAS, EGNOS and MSAS and A-GPS aiding . It is also possible to store the configuration settings in an optional external EEPROM.

The ATR0621P1 is manufactured using the high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator and a wide range of peripheral functions on a monolithic chip, the ATR0621P1 provides a highly-flexible and cost-effective solution for GPS applications.
2 ATR0621P1

Figure Block Diagram

NSHDN NSLEEP

XT_IN XT_OUT

RF_ON CLK23

P15/ANTON P0/NANTSHORT

P14/NAADET1 P25/NAADET0 P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0

P9/EXTINT0 P2/BOOT_MODE

P30/AGCOUT0 P8/STATUSLED

P16/NEEPROM P11/EM_A21 P28/EM_A20

P10/EM_A0/NLB P7/NUB/NWR1 P6/NOE/NRD

P5/NWE/NWR0 P4/nCS0 P3/nCS1 EM_A19 EM_A1

EM_DA15 EM_DA0

DBG_EN NTRST TDI TDO TCK TMS

NRESET

PIO2

Reset Controller

JTAG

Embedded ICE

ARM7TDMI

Interface to Off-Chip Memory EBI

Watchdog

Advanced Interrupt Controller

Special Function

PIO2 Controller

SMD Generator

Advanced Power

Management

Controller

RTC SRAM

Power Supply Manager
Ordering Information

Extended Type Number

Package

ATR0621P1-7FQY

LFBGA100

ATR0621P1-7FHW

ATR0622-EK1 ATR0622-DK1

LFBGA100

Package LFBGA100

Package R-LFBGA 100_G Dimensions in mm

A1 Corner

Top View
1 2 3 4 5 6 7 8 9 10

A B C D E F G H J K

MPQ 2000
2000 1

Remarks
9 mm x 9 mm, mm pitch, ROM5, RoHS-compliant, automotive type
9 mm x 9 mm, mm pitch, ROM5, RoHS-compliant, green, automotive type

Evaluation kit/road test kit

Development kit including example design information
100x

Bottom View

A1 Corner
10 9 8 7 6 5 4 3 2 1
technical drawings according to DIN specifications

A 4x C
ref.

Drawing-No. Issue 2;

Seating plane C

Moisture sensitivity level MSL = 3
12 ATR0621P1

ATR0621P1

History
4975BS-GPS-05/08
• Table 3-1 “ATR0621P1 Pinout” on page 5 Pin type of pin CLK23 changed.

Headquarters

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600

International

Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721-9778 Fax 852 2722-1369

Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ATR0621P-7FQY Datasheet file may be downloaded here without warranties.

Datasheet ID: ATR0621P-7FQY 519278