AT91 ARM Thumb-based Microcontrollers AT91SAM9261S Summary
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AT91SAM9261SB-CU (pdf) |
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• Incorporates the ARM926EJ-S Processor DSP Instruction Extensions ARM Technology for Acceleration 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer 210 MIPS at 190 MHz Memory Management Unit EmbeddedICE , Debug Communication Channel Support Mid-level implementation Embedded Trace Macrocell • Additional Embedded Memories 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed 16 Kbytes of Internal SRAM, Single-cycle Access at Bus Speed • External Bus Interface EBI Supports SDRAM, Static Memory, NAND Flash and • LCD Controller Supports Passive or Active Displays Up to 16-bits per Pixel in STN Color Mode Up to 16M Colors in TFT Mode 24-bit per Pixel , Resolution up to 2048 x 2048 • USB Full Speed 12 Mbits per second Host Double Port • Dual On-chip Transceivers • Integrated FIFOs and Dedicated DMA Channels USB Full Speed 12 Mbits per second Device Port • On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs • Bus Matrix Handles Five Masters and Five Slaves Boot Mode Select Option Remap Command • Fully Featured System Controller SYSC for Efficient System Management, including Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes Clock Generator and Power Management Controller Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer and Real-time Timer Three 32-bit PIO Controllers • Reset Controller RSTC Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control • Shutdown Controller SHDWC Programmable Shutdown Pin Control and Wake-up Circuitry • Clock Generator CKGR 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock 3 to 20 MHz On-chip Oscillator and two PLLs • Power Management Controller PMC Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Four Programmable External Clock Signals AT91 ARM Thumb-based Microcontrollers AT91SAM9261S Summary • Advanced Interrupt Controller AIC Individually Maskable, Eight-level Priority, Vectored Interrupt Sources Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected • Debug Unit DBGU 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention Mode for General Purpose Two-wire UART Serial Communication • Periodic Interval Timer PIT 20-bit Interval Timer plus 12-bit Interval Counter • Watchdog Timer WDT Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock • Real-Time Timer RTT 32-bit Free-running Backup Counter Running at Slow Clock • Three 32-bit Parallel Input/Output Controllers PIO PIOA, PIOB and PIOC 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os Input Change Interrupt Capability on Each I/O Line Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output • Nineteen Peripheral DMA PDC Channels • Multimedia Card Interface MCI SDCard and MultiMediaCard Compliant Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant • Three Synchronous Serial Controllers SSC Independent Clock and Frame Sync Signals for Each Receiver and Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer • Three Universal Synchronous/Asynchronous Receiver Transmitters USART Individual Baud Rate Generator, Infrared Modulation/Demodulation Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support • Two Master/Slave Serial Peripheral Interface SPI 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects • One Three-channel 16-bit Timer/Counters TC Three External Clock Inputs, Two multi-purpose I/O Pins per Channel Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • Two-wire Interface TWI Master Mode Support, All Two-wire Atmel EEPROMs Supported • JTAG Boundary Scan on All Digital Pins • Required Power Supplies 1.08V to 1.32V for VDDCORE and VDDBU 3.0V to 3.6V for VDDOSC and for VDDPLL 2.7V to 3.6V for VDDIOP Peripheral I/Os 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM Memory I/Os • Available in a 217-ball LFBGA RoHS-compliant Package 2 AT91SAM9261S AT91SAM9261S The AT91SAM9261S is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The AT91SAM9261S is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays. The 16 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for LCD refresh on the overall processor performance. The External Bus Interface incorporates controllers for synchronous DRAM SDRAM and Static memories and features specific interface circuitry for CompactFlash and NAND Flash. The AT91SAM9261S integrates a ROM-based Boot Loader supporting code shadowing from, for example, external into external SDRAM. The software controlled Power Management Controller PMC keeps system power consumption to a minimum by selectively enabling/disabling the processor and various peripherals and adjustment of the operating frequency. The AT91SAM9261S also benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel DBGU and an embedded real time trace. This enables the development and debug of all applications, especially those with real-time constraints. Block Diagram Figure AT91SAM9261S Block Diagram JTAGSEL TDI TDO TMS TCK NTRST RTCK TST FIQ IRQ0-IRQ2 DRXD DTXD PCK0-PCK3 PLLRCA PLLRCB XIN XOUT XIN32 XOUT32 SHDN WKUP VDDBU GNDBU VDDCORE NRST MCCK MCCDA MCDA0-MCDA3 RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 RXD2 TXD2 SCK2 RTS2 CTS2 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS10 SPI1_NPCS1 SPI1_NPCS12 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK JTAG Boundary Scan System Controller AIC AT91SAM9261S Ordering Information Table AT91SAM9261S Ordering Information Ordering Code Package AT91SAM9261S-CJ BGA217 AT91SAM9261SB-CU BGA217 Package Type RoHS-compliant RoHS-compliant AT91SAM9261S Temperature Operating Range Industrial -40°C to 85°C Industrial -40°C to 85°C In the table below the most recent version of the datasheet appears first. 6242CS 6242BS 6242AS Comments Section “BMS = 1, Boot on Embedded ROM” updated. “Features” Additional Embedded Memories, 16 Kbytes SRAM updated. Debug Unit DBGU updated. Section “AT91SAM9261S Ordering Information” added to document. First Issue Change Request Ref. 6387 5848 5846 5487 5794 38 AT91SAM9261S Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel 852 2245-6100 Fax 852 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581 Product Contact Web Site Literature Requests Technical Support AT91SAM Support Sales Contacts Disclaimer The information in this document is provided in connection with Atmel products. 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