AT91SAM9XE128-CU

AT91SAM9XE128-CU Datasheet


• Additional Embedded Memories One 32-Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed One 32-Kbyte for AT91SAM9XE256 and AT91SAM9XE512 or 16-Kbyte for AT91SAM9XE128 Internal SRAM, Single-cycle Access at Maximum Matrix Speed 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128, AT91SAM9XE256 or AT91SAM9XE512 Respectively. Organized in 256, 512 or 1024 Pages of 512 Bytes Respectively.<br>• 128-bit Wide Access<br>• Fast Read Time 45 ns<br>• Page Programming Time 4 ms, Including Page Auto-erase, Full Erase Time 10 ms<br>• 10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash Security Bit

Part Datasheet
AT91SAM9XE128-CU AT91SAM9XE128-CU AT91SAM9XE128-CU (pdf)
Related Parts Information
AT91SAM9XE256-QU AT91SAM9XE256-QU AT91SAM9XE256-QU
AT91SAM9XE128-QU AT91SAM9XE128-QU AT91SAM9XE128-QU
AT91SAM9XE512-QU AT91SAM9XE512-QU AT91SAM9XE512-QU
AT91SAM9XE512-CU AT91SAM9XE512-CU AT91SAM9XE512-CU
AT91SAM9XE256-CU AT91SAM9XE256-CU AT91SAM9XE256-CU
PDF Datasheet Preview
• Incorporates the ARM926EJ-S Processor DSP instruction Extensions, ARM Technology for Acceleration 8 Kbytes Data Cache, 16 Kbytes Instruction Cache, Write Buffer 200 MIPS at 180 MHz Memory Management Unit EmbeddedICE , Debug Communication Channel Support
• Additional Embedded Memories One 32-Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed One 32-Kbyte for AT91SAM9XE256 and AT91SAM9XE512 or 16-Kbyte for AT91SAM9XE128 Internal SRAM, Single-cycle Access at Maximum Matrix Speed 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128, AT91SAM9XE256 or AT91SAM9XE512 Respectively. Organized in 256, 512 or 1024 Pages of 512 Bytes Respectively.
• 128-bit Wide Access
• Fast Read Time 45 ns
• Page Programming Time 4 ms, Including Page Auto-erase, Full Erase Time 10 ms
• 10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash Security Bit
• Enhanced Embedded Flash Controller EEFC Interface of the Flash Block with the 32-bit Internal Bus Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory Interface
• External Bus Interface EBI Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash
• USB Full Speed 12 Mbits per second Device Port On-chip Transceiver, 2,688-byte Configurable Integrated DPRAM
• USB Full Speed 12 Mbits per second Host Single Port in the 208-pin PQFP Device and Double Port in 217-ball LFBGA Device Single or Dual On-chip Transceivers Integrated FIFOs and Dedicated DMA Channels
• Ethernet MAC 10/100 Base-T Media Independent Interface or Reduced Media Independent Interface 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
• Image Sensor Interface ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate 12-bit Data Interface for Support of High Sensibility Sensors SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
• Bus Matrix Six 32-bit-layer Matrix Remap Command
• Fully-featured System Controller, including Reset Controller, Shutdown Controller Four 32-bit Battery Backup Registers for a Total of 16 Bytes Clock Generator and Power Management Controller Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer and Real-time Timer

AT91 ARM Thumb Microcontrollers AT91SAM9XE128 AT91SAM9XE256 AT91SAM9XE512 Preliminary
• Reset Controller RSTC Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control
• Clock Generator CKGR Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock 3 to 20 MHz On-chip Oscillator, One Up to 240 MHz PLL and One Up to 100 MHz PLL
• Power Management Controller PMC Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Two Programmable External Clock Signals
• Advanced Interrupt Controller AIC Individually Maskable, Eight-level Priority, Vectored Interrupt Sources Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit DBGU 2-wire UART and support for Debug Communication Channel, Programmable ICE Access Prevention Mode for General Purpose Two-wire UART Serial Communication
• Periodic Interval Timer PIT 20-bit Interval Timer Plus 12-bit Interval Counter
• Watchdog Timer WDT Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
• Real-Time Timer RTT 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
• One 4-channel 10-bit Analog to Digital Converter
• Three 32-bit Parallel Input/Output Controllers PIOA, PIOB, PIOC,
96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os Input Change Interrupt Capability on Each I/O Line Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
• Peripheral DMA Controller Channels PDC
• Two-slot Multimedia Card Interface MCI SDCard/SDIO and MultiMediaCard Compliant Automatic Protocol Control and Fast Automatic Data Transfers with PDC
• One Synchronous Serial Controllers SSC Independent Clock and Frame Sync Signals for Each Receiver and Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Four Universal Synchronous/Asynchronous Receiver Transmitters USART Individual Baud Rate Generator, Infrared Modulation/Demodulation, Manchester Encoding/Decoding Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Full Modem Signal Control on USART0
• One 2-wire UART
• Two Master/Slave Serial Peripheral Interface SPI 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects Synchronous Communications
• Two Three-channel 16-bit Timer/Counters TC Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel Double PWM Generation, Capture/Waveform Mode, Up/Down Capability High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2
• Two-wire Interfaces TWI Master, Multi-master and Slave Mode Operation General Call Supported in Slave Mode Connection to PDC Channel to Optimize Data Transfers in Master Mode Only
2 AT91SAM9XE128/256/512 Preliminary

AT91SAM9XE128/256/512 Preliminary
• JTAG Boundary Scan on All Digital Pins
• Required Power Supplies:
1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL 1.65V to 3.6V for VDDIOP1 Peripheral I/Os 3.0V to 3.6V for VDDIOP0 and VDDANA Analog-to-digital Converter Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM Memory I/Os
• Available in a 208-pin PQFP Green and a 217-ball LFBGA Green Package

AT91SAM9XE128/256/512 Description

The AT91SAM9XE128/256/512 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM, 128, 256 or 512 Kbytes of Flash and a wide range of peripherals. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits a security bit and MMU protect the firmware from accidental overwrite and preserve its confidentiality. The AT91SAM9XE128/256/512 embeds an Ethernet MAC, one USB Device Port, and a USB Host Controller. It also integrates several standard peripherals, like six UARTs, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and a MultiMedia/SD Card Interface. The AT91SAM9XE128/256/512 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator. The AT91SAM9XE128/256/512 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide range of memory devices. The pinout and ball-out are fully compatible with the AT91SAM9260 with the exception that the pin BMS is replaced by the pin ERASE.

AT91SAM9XE128/256/512 Block Diagram

The block diagram shows all the features for the 217-LFBGA package. Some functions are not accessible in the 208-PQFP package and the unavailable pins are highlighted in “Multiplexing on PIO Controller A” on page 36, “Multiplexing on PIO Controller B” on page 37, “Multiplexing on PIO Controller C” on page The USB Host Port B is also not available. Table 2-1 on page 4 defines all the multiplexed and not multiplexed pins not available in the 208-PQFP package.

Table Unavailable Signals in 208-pin PQFP Device

Peripheral A

Peripheral B

HDPB

HDMB

PA30

SCK2

RXD4

PA31

SCK0

TXD4

PB12
Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding.

All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format.

Table Mode Default Mode1 Mode2 Mode3
Data Ordering in YCbCr Mode

Byte 0

Byte 1

Byte 2 Cr i Cb i Y i+1 Y i+1

Byte 3 Y i+1 Y i+1 Cr i Cb i

Table Mode RGB 8:8:8

RGB 5:6:5

RGB Format in Default Mode, RGB_CFG = 00, No Swap

Byte

Byte 0

Byte 1

Byte 2

Byte 3

R7 i+1 R6 i+1 R5 i+1 R4 i+1

Byte 0

Byte 1

Byte 2

R4 i+1 R3 i+1 R2 i+1 R1 i+1

Byte 3

G2 i+1 G1 i+1 G0 i+1 B4 i+1

D3 R3 i G3 i B3 i R3 i+1 R0 i B3 i R0 i+1 B3 i+1

D2 R2 i G2 i B2 i R2 i+1 G5 i B2 i G5 i+1 B2 i+1

D1 R1 i G1 i B1 i R1 i+1 G4 i B1 i G4 i+1 B1 i+1

D0 R0 i G0 i B0 i R0 i+1 G3 i B0 i G3 i+1 B0 i+1

Table Mode

RGB 5:6:5

RGB Format, RGB_CFG = 10 Mode 2 , No Swap

Byte

Byte 0

Byte 1

Byte 2

G2 i+1 G1 i+1 G0 i+1 R4 i+1

Byte 3

B4 i+1 B3 i+1 B2 i+1 B1 i+1

D3 R3 i B0 i R3 i+1 B0 i+1

D2 R2 i G5 i R2 i+1 G5 i+1

D1 R1 i G4 i R1 i+1 G4 i+1

D0 R0 i G3 i R0 i+1 G3 i+1
752 AT91SAM9XE128/256/512 Preliminary

AT91SAM9XE128/256/512 Preliminary

Table Mode RGB 8:8:8
AT91SAM9XE128/256/512 Ordering Information
Table AT91SAM9XE128/256/512 Ordering Information
Ordering Code

Package

Package Type

AT91SAM9XE128-QU

PQFP208

Green

AT91SAM9XE128-CU

BGA217

Green

AT91SAM9XE256-QU

PQFP208

Green

AT91SAM9XE256-CU

BGA217

Green

AT91SAM9XE512-QU

PQFP208

Green

AT91SAM9XE512-CU

BGA217

Green

Temperature Operating Range

Industrial -40°C to 85°C

Industrial -40°C to 85°C

Industrial -40°C to 85°C
836 AT91SAM9XE128/256/512 Preliminary

AT91SAM9XE128/256/512 Preliminary

AT91SAM9XE128/256/512 Errata

Marking
All devices are marked with the Atmel logo and the ordering code. Additional marking may be in one of the following formats:

YYWW V
where

Refer to Section “Marking” on page

Analog-to-Digital Converter ADC

ADC Sleep Mode If Sleep mode is activated while there is no activity no conversion is being performed , it will take effect only after a conversion occurs.

Problem Fix/Workaround To activate sleep mode as soon as possible, it is recommended to write successively, ADC Mode Register SLEEP then ADC Control Register START bit field , in order to start an analogto-digital conversion and then put ADC into sleep mode at the end of this conversion.

Error Corrected Code Controller ECC

ECC Computation with a 1 clock cycle long NRD/NWE pulse If the SMC is programmed with NRD/NWE pulse length equal to 1 clock cycle, HECC can't compute the parity.

Problem/Fix Workaround It is recommended to program SMC with a value higher than

MultiMedia Card Interface MCI

MCI Busy signal of R1b responses is not taken in account The busy status of the card during the response R1b is ignored for the commands CMD7, CMD28, CMD29, CMD38, CMD42, CMD56. Additionally, for commands CMD42 and CMD56 a conflict can occur on data line0 if the MCI sends data to the card while the card is still busy. The behavior is correct for CMD12 command STOP_TRANSFER .

Problem Fix/Workaround None

MCI SDIO Interrupt does not work with slots other than A If there is 1-bit data bus width on slots other than slot A, the SDIO interrupt can not be captured. The sample is made on the wrong data line.

Problem Fix/Workaround

None

MCI Data Write Operation and number of bytes The Data Write operation with a number of bytes less than 12 is impossible.

Problem Fix/Workaround The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The BLKLEN or BCNT field are used to specify the real count number.

MCI Flag Reset is not correct in half duplex mode In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be incorrect. These flags are reset correctly after a PDC channel enable.

Problem Fix/Workaround
838 AT91SAM9XE128/256/512 Preliminary

AT91SAM9XE128/256/512 Preliminary

Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the PDC channel by writing PDC_TXTEN or PDC_RXTEN.

MCI Small Block Reading In case of a read of a small block i.e., 5 bytes by the READ_SINGLE_BLOCK command CMD17 , the DATA FSM may not perform correctly. This occurs if the read transfer is done before the response start bit is sent by the card. It leads to erratic behavior of the NOTBUSY flag and to a false data time-out error, DTOE.

Problem Fix/Workaround None.

MCI old SDCard Compatibility Busy line is sampled 2 clock cycles after the command End Bit when the R1B response type is expected. This timing is not strictly defined in SD mode.

This timing is defined with MMC specification R1b Busy Timing

Problem Fix/Workaround None.

Reset Controller RSTC

RSTC Reset Type Status is wrong at power-up RSTTYP status in the Reset Controller Status Register is wrong at power-up.

It should be “0” General Reset but it is “5” Brownout Reset . The value is the same if Brownout and Brownout Reset are enabled or not. The BODSTS bit remains correct.

Problem Fix/Workaround None.

Static Memory Controller SMC

SMC Chip Select Parameters Modification The user must not change the configuration parameters of an SMC Chip Select Setup, Pulse, Cycle, Mode if accesses are performed on this CS during the modification.

For example, the modification of the Chip Select 0 CS0 parameters, while fetching the code from a memory connected on this CS0, may lead to unpredictable behavior.

Problem Fix/Workaround The code used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory connected to another Chip Select.

Serial Peripheral Interface SPI

SPI Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0 If the SPI is used in the following configuration:
• master mode
• CPOL = 1 and NCPHA = 0
• multiple chip selects used with one transfer with Baud rate SCBR equal to 1 i.e., when
serial clock frequency equals the system clock frequency and the other transfers set with SCBR not equal to 1
• transmit with the slowest chip select and then with the fastest one, then an additional pulse will be generated on output SPCK during the second transfer.

Problem Fix/Workaround Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and the others differ from 1 if CPHA = 0 and CPOL =
45 AT91SAM9XE128/256/512 Ordering Information 836 46 AT91SAM9XE128/256/512 Errata 837

Headquarters

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600

International

Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel 852 2245-6100 Fax 852 2722-1369

Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11

Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581

Product Contact

Web Site

Technical Support AT91SAM Support

Literature Requests

Sales Contacts

Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
2010 Atmel Corporation. All rights reserved. Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. the logo, and others are registered trademarks or trademarks of ARM Ltd. and others are registered trademarks or trademarks of Microsoft Corporation in the US and/or in other countries. Other terms and product names may be the trademarks of others.
More datasheets: 2114 | FFPF15UP20STTU | AOW410 | FQD4N20LTM | FQD4N20LTF | 46448-00000 | CSD10030A | AT91SAM9XE256-QU | AT91SAM9XE128-QU | AT91SAM9XE512-QU


Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT91SAM9XE128-CU Datasheet file may be downloaded here without warranties.

Datasheet ID: AT91SAM9XE128-CU 519133