Single Cycle Reprogram Erase and Program 8192 Pages 528 Bytes/Page Main Memory<br>• Supports Page and Block Erase Operations<br>• Two 528-byte SRAM Data Buffers Allows Receiving of Data while Reprogramming of Nonvolatile Memory<br>• Continuous Read Capability through Entire Array Ideal for Code Shadowing Applications<br>• Low Power Dissipation 4 mA Active Read Current Typical 2 µA CMOS Standby Current Typical<br>• Hardware Data Protection Feature<br>• 100% Compatible to AT45DB321<br>• 5.0V-tolerant Inputs SI, SCK, CS, RESET and WP Pins<br>• Commercial and Industrial Temperature Ranges
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AT45DB321B-TI (pdf) |
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AT45DB321B-CI |
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AT45DB321B-RI |
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AT45DB321B-RC |
PDF Datasheet Preview |
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• Single 2.7V - 3.6V Supply • Serial Peripheral Interface SPI Compatible • 20 MHz Max Clock Frequency • Page Program Operation Single Cycle Reprogram Erase and Program 8192 Pages 528 Bytes/Page Main Memory • Supports Page and Block Erase Operations • Two 528-byte SRAM Data Buffers Allows Receiving of Data while Reprogramming of Nonvolatile Memory • Continuous Read Capability through Entire Array Ideal for Code Shadowing Applications • Low Power Dissipation 4 mA Active Read Current Typical 2 µA CMOS Standby Current Typical • Hardware Data Protection Feature • 100% Compatible to AT45DB321 • 5.0V-tolerant Inputs SI, SCK, CS, RESET and WP Pins • Commercial and Industrial Temperature Ranges The AT45DB321B is a 2.7-volt only, serial interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In addition to the main memor y, the AT45DB321B also contains two SRAM data buffers of 528 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed, as well as reading or writing a continuous data Pin Configurations Pin Name Function Chip Select Serial Clock Serial Input Serial Output Hardware Page Write Protect Pin RESET Chip Reset RDY/BUSY Ready/Busy CBGA Top View through Package 12345 D NC SCK GND VCC NC E NC CS RDY/BSY WP NC F NC SO SI RESET NC 32-megabit 2.7-volt Only AT45DB321B SOIC RESET RDY/BUSY TSOP Top View Type 1 RDY/BUSY 1 RESET 2 WP 3 NC 4 NC 5 NC 6 VCC 7 GND 8 NC 9 NC 10 NC 11 NC 12 CS 13 SCK 14 SI 15 SO 16 32 NC 31 NC 30 NC 29 NC 28 NC 27 NC 26 NC 25 NC 24 NC 23 NC 22 NC 21 NC 20 NC 19 NC 18 NC 17 NC Note: DataFlash Card 1 7654321 See AT45DCB004 Datasheet Block Diagram Memory Array stream. EEPROM emulation bit or byte alterability is easily handled with a self-contained three step Read-Modify-Write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a SPI serial interface to sequentially access its data. DataFlash supports SPI mode 0 and mode The simple serial interface facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size and active pin count. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. The device operates at clock frequencies up to 20 MHz with a typical active read current consumption of 4 mA. To allow for simple in-system reprogrammability, the AT45DB321B does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321B is enabled through the chip select pin CS and accessed via a three-wire interface consisting of the Serial Input SI , Serial Output SO , and the Serial Clock SCK . All programming cycles are self-timed, and no separate erase cycle is required before programming. When the device is shipped from Atmel, the most significant page of the memory array may not be erased. In other words, the contents of the last page may not be filled with FFH. FLASH MEMORY ARRAY PAGE 528 BYTES BUFFER 1 528 BYTES BUFFER 2 528 BYTES SCK CS RESET VCC GND Ordering Information fSCK MHz ICC mA Active Standby Ordering Code AT45DB321B-CC AT45DB321B-RC AT45DB321B-TC AT45DB321B-CI AT45DB321B-RI AT45DB321B-TI Package 44C1 28R 32T 44C1 28R 32T Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C 44C1 28R 32T Package Type 44-ball 5 x 9 Array , mm Pitch, Plastic Chip-scale Ball Grid Array CBGA 28-lead, Wide, Plastic Gull Wing Small Outline Package SOIC 32-lead, Plastic Thin Small Outline Package TSOP 28 AT45DB321B Packaging Information 44C1 CBGA AT45DB321B Dimensions in Millimeters and Inches . Controlling dimension Millimeters. A1 ID SIDE VIEW TOP VIEW 0.010 MIN MAX 0.039 REF 54 3 21 0.079 REF NON-ACCUMULATIVE BSC NON-ACCUMULATIVE DIA BALL TYP BOTTOM VIEW TITLE 2325 Orchard Parkway 44C1, 44-ball 5 x 9 Array , 6 x 12 x mm Body, mm Ball R San Jose, CA 95131 Pitch Chip-scale Ball Grid Array Package CBGA 04/11/01 44C1 32T TSOP PIN 1 0º ~ 8º c Pin 1 Identifier SEATING PLANE GAGE PLANE This package conforms to JEDEC reference MO-142, Variation BD. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum. COMMON DIMENSIONS Unit of Measure = mm SYMBOL A A1 A2 D D1 E L L1 b c e MIN NOM MAX BASIC BASIC |
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