AT32UC3L0-XPLD

AT32UC3L0-XPLD Datasheet

32-bit Microcontroller AT32UC3L064 AT32UC3L032 AT32UC3L016 Preliminary

Part	Datasheet
AT32UC3L0-XPLD	AT32UC3L0-XPLD (pdf)

PDF Datasheet Preview
• High Performance, Low Power 32-bit Microcontroller Compact Single-cycle RISC Instruction Set including DSP Instructions Read Modify Write Instructions and Atomic Bit Manipulation Performance • Up to 64DMIPS Running at 50MHz from Flash 1 Flash Wait State • Up to 36DMIPS Running at 25MHz from Flash 0 Flash Wait State Memory Protection Unit MPU • Secure Access Unit SAU providing User Defined Peripheral Protection • Technology for Ultra-low Power Consumption • Multi-hierarchy Bus System High-performance Data Transfers on Separate Buses for Increased Performance 12 Peripheral DMA Channels improve Speed for Peripheral Communication • Internal High-speed Flash 64Kbytes, 32Kbytes, and 16Kbytes Versions Single-cycle Access up to 25MHz FlashVault Technology Allows Pre-programmed Secure Library Support for End User Applications Prefetch Buffer Optimizing Instruction Execution at Maximum Speed 100,000 Write Cycles, 15-year Data Retention Capability Flash Security Locks and User Defined Configuration Area • Internal High-speed SRAM, Single-cycle Access at Full Speed 16Kbytes 64Kbytes and 32Kbytes Flash , or 8Kbytes 16Kbytes Flash • Interrupt Controller INTC Autovectored Low Latency Interrupt Service with Programmable Priority • External Interrupt Controller EIC • Peripheral Event System for Direct Peripheral to Peripheral Communication • System Functions Power and Clock Manager SleepWalking Power Saving Control Internal System RC Oscillator RCSYS 32KHz Oscillator Multipurpose Oscillator and Digital Frequency Locked Loop DFLL • Windowed Watchdog Timer WDT • Asynchronous Timer AST with Real-time Clock Capability Counter or Calendar Mode Supported • Frequency Meter FREQM for Accurate Measuring of Clock Frequency • Six 16-bit Timer/Counter TC Channels External Clock Inputs, PWM, Capture and Various Counting Capabilities • PWM Channels on All I/O Pins PWMA 8-bit PWM up to 150MHz Source Clock • Four Universal Synchronous/Asynchronous Receiver/Transmitters USART Independent Baudrate Generator, Support for SPI Support for Hardware Handshaking • One Master/Slave Serial Peripheral Interfaces SPI with Chip Select Signals Up to 15 SPI Slaves can be Addressed • Two Master and Two Slave Two-wire Interface TWI , 400kbit/s I2C-compatible • One 8-channel Analog-to-digital Converter ADC with up to 12 Bits Resolution Internal Temperature Sensor 32-bit Microcontroller AT32UC3L064 AT32UC3L032 AT32UC3L016 Preliminary AT32UC3L016/32/64 • Eight Analog Comparators AC with Optional Window Detection • Capacitive Touch CAT Module Hardware Assisted and Touch Acquisition Supports QTouch and QMatrix Capture from Capacitive Touch Sensors • QTouch Library Support Capacitive Touch Buttons, Sliders, and Wheels QTouch and QMatrix Acquisition • On-chip Non-intrusive Debug System Nexus Class 2+, Runtime Control, Non-intrusive Data and Program Trace aWire Single-pin Programming Trace and Debug Interface Muxed with Reset Pin NanoTrace Provides Trace Capabilities through JTAG or aWire Interface • 48-pin TQFP/QFN/TLLGA 36 GPIO Pins • Five High-drive I/O Pins • Single V Power Supply AT32UC3L016/32/64 The AT32UC3L is a complete System-on-chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance. The processor implements a Memory Protection Unit MPU and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. The Secure Access Unit SAU is used together with the MPU to provide the required security and integrity. Higher computation capability is achieved using a rich set of DSP instructions. The AT32UC3L embeds state-of-the-art picoPower technology for ultra-low power consumption. Combined power control techniques are used to bring active current consumption down to 165µA/MHz, and leakage down to 9nA while still retaining a bank of backup registers. The device allows a wide range of trade-offs between functionality and power consumption, giving the user the ability to reach the lowest possible power consumption with the feature set required for the application. The Peripheral Direct Memory Access DMA controller enables data transfers between peripherals and memories without processor involvement. The Peripheral DMA controller drastically reduces processing overhead when transferring continuous and large data streams. The AT32UC3L incorporates on-chip Flash and SRAM memories for secure and fast access. The FlashVault technology allows secure libraries to be programmed into the device. The secure libraries can be executed while the CPU is in Secure State, but not read by non-secure software in the device. The device can thus be shipped to end costumers, who will be able to program their own code into the device, accessing the secure libraries, but without risk of compromising the proprietary secure code. The Peripheral Event System allows peripherals to receive, react to, and send peripheral events without CPU intervention. Asynchronous interrupts allow advanced peripheral operation in low power sleep modes. The Power Manager improves design flexibility and security. The Power Manager supports SleepWalking functionality, by which a module can be selectively activated based on peripheral events, even in sleep modes where the module clock is stopped. Power monitoring is supported by on-chip Power-on Reset POR , Brown-out Detector BOD , and Supply Monitor SM . The device features several oscillators, such as Digital Frequency Locked Loop DFLL , Oscillator 0 OSC0 , and system RC oscillator RCSYS . Either of these oscillators can be used as source for the system clock. The DFLL is a programmable internal oscillator from 40 to 150MHz. It can be tuned to a high accuracy if an accurate oscillator is running, e.g. the 32KHz crystal oscillator. The Watchdog Timer WDT will reset the device unless it is periodically serviced by the software. This allows the device to recover from a condition that has caused the system to be unstable. The Asynchronous Timer AST combined with the 32KHz crystal oscillator supports powerful real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in counter mode or calendar mode. The Frequency Meter FREQM allows accurate measuring of a clock frequency by comparing it to a known reference clock. AT32UC3L016/32/64 The device includes six identical 16-bit Timer/Counter TC channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. The Pulse Width Modulation controller PWMA provides 8-bit PWM channels which can be synchronized and controlled from a common timer. One PWM channel is available for each I/O pin on the device, enabling applications that require multiple PWM outputs, such as LCD backlight control. The PWM channels can operate independently, with duty cycles set independently from each other, or in interlinked mode, with multiple channels changed at the same time. The AT32UC3L also features many communication interfaces for communication intensive applications like USART, SPI, or TWI. The USART supports different communication modes, like SPI Mode and LIN Mode. A general purpose 8-channel ADC is provided, as well as eight analog comparators AC . The ADC can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering up to 12-bit resolution. The ADC also provides an internal temperature sensor input channel. The analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. The Capacitive Touch CAT module senses touch on external capacitive touch sensors, using the QTouch technology. Capacitive touch sensors use no external mechanical components, unlike normal push buttons, and therefore demand less maintenance in the user application. The CAT module allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced. One touch sensor can be configured to operate autonomously without software interaction, allowing wakeup from sleep modes when activated. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys as well as Adjacent Key technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications. The AT32UC3L integrates a class 2+ Nexus On-chip Debug OCD System, with non-intrusive real-time trace, full-speed read/write memory access, in addition to basic runtime control. The NanoTrace interface enables trace feature for aWire- or JTAG-based debuggers. The single-pin aWire interface allows all features available through the JTAG interface to be accessed through the RESET pin, allowing the JTAG pins to be used for GPIO or peripherals. AT32UC3L016/32/64 Overview Block Diagram Figure Block Diagram TCK TDO TDI TMS DATAOUT RESET_N MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N JTAG INTERFACE aWire NEXUS CLASS 2+ AVR32UC CPU MEMORY PROTECTION UNIT INSTR DATA INTERFACE MEMORY INTERFACE LOCAL BUS INTERFACE LOCAL BUS If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 4-4 on page If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority AT32UC3L016/32/64 than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4 on page Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floatingpoint unit. AT32UC3L016/32/64 Table Priority and Handler Addresses for Events Priority Handler Address Name Reset Provided by OCD system OCD Stop CPU EVBA+0x00 Unrecoverable exception EVBA+0x04 TLB multiple hit EVBA+0x08 Bus error data fetch EVBA+0x0C Bus error instruction fetch EVBA+0x10 Autovectored Interrupt 3 request Autovectored Interrupt 2 request Autovectored Interrupt 1 request Autovectored Interrupt 0 request EVBA+0x14 Instruction Address EVBA+0x50 ITLB Miss EVBA+0x18 ITLB Protection EVBA+0x1C Breakpoint EVBA+0x20 Illegal Opcode EVBA+0x24 Unimplemented instruction EVBA+0x28 Privilege violation Ordering Information Table Ordering Information Device AT32UC3L064 AT32UC3L032 AT32UC3L016 Ordering Code AT32UC3L064-AUTES AT32UC3L064-AUT AT32UC3L064-AUR AT32UC3L064-ZAUES AT32UC3L064-ZAUT AT32UC3L064-ZAUR AT32UC3L064-D3HES AT32UC3L064-D3HT AT32UC3L064-D3HR AT32UC3L032-AUT AT32UC3L032-AUR AT32UC3L032-ZAUT AT32UC3L032-ZAUR AT32UC3L032-D3HT AT32UC3L032-D3HR AT32UC3L016-AUT AT32UC3L016-AUR AT32UC3L016-ZAUT AT32UC3L016-ZAUR AT32UC3L016-D3HT AT32UC3L016-D3HR Carrier Type ES Tray Tape & Reel ES Tray Tape & Reel ES Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Package TQFP 48 QFN 48 TLLGA 48 TQFP 48 QFN 48 TLLGA 48 TQFP 48 QFN 48 TLLGA 48 Package Type Temperature Operating Range JESD97 Classification E3 JESD97 Classification E4 Industrial -40°C to 85°C JESD97 Classification E3 JESD97 Classification E4 JESD97 Classification E3 JESD97 Classification E4 AT32UC3L016/32/64 Errata Processor and Architecture Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception will occur. Fix/Workaround Make a DTLB Protection Write exception handler which permits the interrupt request to be handled in privileged mode. FLASHCDW Flash self programming may fail in one wait state mode Writes in flash and user pages may fail if executing code is located in address space mapped to flash, and the flash controller is configured in one wait state mode the Flash Wait State bit in the Flash Control Register FCR.FWS is one . Fix/Workaround Solution 1 Configure the flash controller in zero wait state mode FCR.FWS=0 . Solution 2 Configure the HMATRIX master 1 CPU Instruction to use the unlimited burst length transfer mode MCFG1.ULBT=0 , and the HMATRIX slave 0 FLASHCDW to use the maximum slot cycle limit SCFG0.SLOT_CYCLE=255 . Power Manager Clock sources will not be stopped in Static mode if the difference between CPU and PBx division factor is larger than 4 If the division factor between the CPU/HSB and PBx frequencies is more than 4 when entering a sleep mode where the system RC oscillator RCSYS is turned off, the high speed clock sources will not be turned off. This will result in a significantly higher power consumption during the sleep mode. Fix/Workaround Before going to sleep modes where RCSYS is stopped, make sure the division factor between CPU/HSB and PBx frequencies is less than or equal to Clock Failure Detector CFD can be issued while turning off the CFD While turning off the CFD, the CFD bit in the Status Register SR can be set. This will change the main clock source to RCSYS. Fix/Workaround Solution 1 Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch back to original main clock source. Solution 2 Only turn off the CFD while running the main clock on RCSYS. Sleepwalking in idle and frozen sleep mode will mask all other PB clocks SCIF AST AT32UC3L016/32/64 If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walking, all PB clocks will be masked except the PB clock to the sleepwalking module. Fix/Workaround Mask all clock requests in the PM.PPCR register before going into idle or frozen mode. The FLO lock bit FLOCR.LOCK does not work The FLO lock bit does not work and will always read as zero. Fix/Workaround Wait for 32 reference clock cycles after the tuner is enabled, then read the FLO.NOLOCK bit to check if it is set. If it is set, a lock can not be obtained for this configuration of reference clock and target ratio. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K is disabled. Fix/Workaround When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit. If this bit is 0 Follow normal procedures. 1 Ignore the PCLKSR.OSC32RDY and ISR.OSC32RDY bit. Use the Frequency Meter FREQM to determine if the OSC32K clock is ready. The OSC32K clock is ready when the FREQM measures a non-zero frequency. The RC32K output on PA20 is not always permanently disabled The RC32K output on PA20 may sometimes re-appear. Fix/Workaround Before using RC32K for other purposes, the following procedure has to be followed in order to properly disable it - Run the CPU on RCSYS - Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT - Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as one - Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as zero. Reset may set status bits in the AST If a reset occurs and the AST is enabled, the SR.ALARM0, SR.PER0, and SR.OVF bits may be set. Fix/Workaround If the part is reset and the AST is used, clear all bits in the Status Register before entering sleep mode. AST wake signal is released one AST clock cycle after the BUSY bit is cleared After writing to the Status Clear Register SCR the wake signal is released one AST clock cycle after the BUSY bit in the Status Register SR.BUSY is cleared. If entering sleep mode directly after the BUSY bit is cleared the part will wake up immediately. Fix/Workaround Read the Wake Enable Register WER and write this value back to the same register. Wait for BUSY to clear before entering sleep mode. Ordering Information Ordering code for TQFP ES changed from AT32UC3L064-AUES to AT32UC3L064-AUTES. TLLGA48 Tray option added. Features and Description Added QTouch library support. USART Description of unimplemented features removed. Electrical Characteristics Power Consumption numbers updated. Flash timing numbers added. Package and Pinout Added pinout figure for TLLGA48 package. Package and Pinout, GPIO function multiplexing:TWIMS0-TWCK on PA20 removed. ADCIFB- AD[3] on PA17 removed, number of ADC channels are 8, not I/O Lines Considerations Added Following pins have high-drive capability PA02, PA06, PA08, PA09, and PB01. Some TWI0 pins are SMBUS compliant PA21, PB04, PB05 . HMATRIX Masters PDCA is master 4, not master SAU is master 3, not master SAU IDLE bit added in the Status Register. PDCA Number of PDCA performance monitors is device dependent. Peripheral Event System Chapter updated. PM Bits in RCAUSE registers removed and renamed JTAGHARD and AWIREHARD renamed to JTAG and AWIRE respectively, JTAG and AWIRE removed. BOD33 bit removed . PM RCAUSE.BOD33 bit removed. SM33 reset will be detected as a POR reset. PM WDT can be used as wake-up source if WDT is clocked from 32KHz oscillator. PM Entering Shutdown mode description updated. SCIF DFLL output frequency is 40-150MHz, not 20-150MHz or 30-150MHz. AT32UC3L016/32/64 SCIF Temperature sensor is connected to ADC channel 9, not SCIF Updated the oscillator connection figure for OSC0 GPIO Removed unimplemented features pull-down, buskeeper, drive strength, slew rate, Schmidt trigger, open drain . SPI RDR.PCS field removed RDR[19:16] . TWIS Figures updated. ADCIFB The sample and hold time and the startup time formulas have been corrected ADC Configuration Register . ADCIFB Updated ADC signal names. ACIFB CONFW.WEVSRC is bit 8-10, CONFW.EWEVEN is bit CONF.EVENP and CONF.EVENN bits are swapped. CAT Matrix size is 16 by 8, not 18 by Electrical Characteristics General update. Mechanical Characteristics Added numbers for package drawings. Mechanical Characteristics In the TQFP-48 package drawing the Lead Coplanarity is 0.102mm, not 0.080mm. Ordering Information Ordering code for TLLGA-48 package updated. AT32UC3L016/32/64 Table of Contents Features 1 Description 3 2 Overview 5 Block Diagram Configuration Summary 3 Package and Pinout 7 Package Peripheral Multiplexing on I/O lines Signal Descriptions I/O Line Considerations 4 Processor and Architecture 18 Features AVR32 Architecture The AVR32UC CPU Programming Model Exceptions and Interrupts 5 Memories 32 Embedded Memories Physical Memory Map Peripheral Address Map CPU Local Bus Mapping 6 Supply and Startup Considerations 36 Supply Considerations Startup Considerations 7 Electrical Characteristics 41 Disclaimer Absolute Maximum Ratings* Supply Characteristics Maximum Clock Frequencies Power Consumption I/O Pin Characteristics Oscillator Characteristics AT32UC3L016/32/64 Flash Characteristics Analog Characteristics Timing Characteristics 8 Mechanical Characteristics 73 Thermal Considerations Package Drawings Soldering Profile 9 Ordering Information 78 10 Errata 79 Table of i Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel 852 2245-6100 Fax 852 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581 Product Contact Web Site Literature Requests Technical Support Sales Contact Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 2011 Atmel Corporation. All rights reserved. Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

PDF Datasheet Preview

• High Performance, Low Power 32-bit Microcontroller Compact Single-cycle RISC Instruction Set including DSP Instructions Read Modify Write Instructions and Atomic Bit Manipulation Performance
• Up to 64DMIPS Running at 50MHz from Flash 1 Flash Wait State
• Up to 36DMIPS Running at 25MHz from Flash 0 Flash Wait State Memory Protection Unit MPU
• Secure Access Unit SAU providing User Defined Peripheral Protection
• Technology for Ultra-low Power Consumption
• Multi-hierarchy Bus System

High-performance Data Transfers on Separate Buses for Increased Performance 12 Peripheral DMA Channels improve Speed for Peripheral Communication
• Internal High-speed Flash 64Kbytes, 32Kbytes, and 16Kbytes Versions Single-cycle Access up to 25MHz FlashVault Technology Allows Pre-programmed Secure Library Support for End

User Applications Prefetch Buffer Optimizing Instruction Execution at Maximum Speed 100,000 Write Cycles, 15-year Data Retention Capability Flash Security Locks and User Defined Configuration Area
• Internal High-speed SRAM, Single-cycle Access at Full Speed 16Kbytes 64Kbytes and 32Kbytes Flash , or 8Kbytes 16Kbytes Flash
• Interrupt Controller INTC Autovectored Low Latency Interrupt Service with Programmable Priority
• External Interrupt Controller EIC
• Peripheral Event System for Direct Peripheral to Peripheral Communication
• System Functions Power and Clock Manager SleepWalking Power Saving Control Internal System RC Oscillator RCSYS 32KHz Oscillator Multipurpose Oscillator and Digital Frequency Locked Loop DFLL
• Windowed Watchdog Timer WDT
• Asynchronous Timer AST with Real-time Clock Capability Counter or Calendar Mode Supported
• Frequency Meter FREQM for Accurate Measuring of Clock Frequency
• Six 16-bit Timer/Counter TC Channels External Clock Inputs, PWM, Capture and Various Counting Capabilities
• PWM Channels on All I/O Pins PWMA 8-bit PWM up to 150MHz Source Clock
• Four Universal Synchronous/Asynchronous Receiver/Transmitters USART Independent Baudrate Generator, Support for SPI Support for Hardware Handshaking
• One Master/Slave Serial Peripheral Interfaces SPI with Chip Select Signals Up to 15 SPI Slaves can be Addressed
• Two Master and Two Slave Two-wire Interface TWI , 400kbit/s I2C-compatible
• One 8-channel Analog-to-digital Converter ADC with up to 12 Bits Resolution Internal Temperature Sensor
32-bit Microcontroller AT32UC3L064 AT32UC3L032 AT32UC3L016 Preliminary

AT32UC3L016/32/64
• Eight Analog Comparators AC with Optional Window Detection
• Capacitive Touch CAT Module

Hardware Assisted and Touch Acquisition Supports QTouch and QMatrix Capture from Capacitive Touch Sensors
• QTouch Library Support Capacitive Touch Buttons, Sliders, and Wheels QTouch and QMatrix Acquisition
• On-chip Non-intrusive Debug System Nexus Class 2+, Runtime Control, Non-intrusive Data and Program Trace aWire Single-pin Programming Trace and Debug Interface Muxed with Reset Pin NanoTrace Provides Trace Capabilities through JTAG or aWire Interface
• 48-pin TQFP/QFN/TLLGA 36 GPIO Pins
• Five High-drive I/O Pins
• Single V Power Supply

AT32UC3L016/32/64

The AT32UC3L is a complete System-on-chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance.

The processor implements a Memory Protection Unit MPU and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. The Secure Access Unit SAU is used together with the MPU to provide the required security and integrity.

Higher computation capability is achieved using a rich set of DSP instructions.

The AT32UC3L embeds state-of-the-art picoPower technology for ultra-low power consumption. Combined power control techniques are used to bring active current consumption down to 165µA/MHz, and leakage down to 9nA while still retaining a bank of backup registers. The device allows a wide range of trade-offs between functionality and power consumption, giving the user the ability to reach the lowest possible power consumption with the feature set required for the application.

The Peripheral Direct Memory Access DMA controller enables data transfers between peripherals and memories without processor involvement. The Peripheral DMA controller drastically reduces processing overhead when transferring continuous and large data streams.

The AT32UC3L incorporates on-chip Flash and SRAM memories for secure and fast access. The FlashVault technology allows secure libraries to be programmed into the device. The secure libraries can be executed while the CPU is in Secure State, but not read by non-secure software in the device. The device can thus be shipped to end costumers, who will be able to program their own code into the device, accessing the secure libraries, but without risk of compromising the proprietary secure code.

The Peripheral Event System allows peripherals to receive, react to, and send peripheral events without CPU intervention. Asynchronous interrupts allow advanced peripheral operation in low power sleep modes.

The Power Manager improves design flexibility and security. The Power Manager supports SleepWalking functionality, by which a module can be selectively activated based on peripheral events, even in sleep modes where the module clock is stopped. Power monitoring is supported by on-chip Power-on Reset POR , Brown-out Detector BOD , and Supply Monitor SM . The device features several oscillators, such as Digital Frequency Locked Loop DFLL , Oscillator 0 OSC0 , and system RC oscillator RCSYS . Either of these oscillators can be used as source for the system clock. The DFLL is a programmable internal oscillator from 40 to 150MHz. It can be tuned to a high accuracy if an accurate oscillator is running, e.g. the 32KHz crystal oscillator.

The Watchdog Timer WDT will reset the device unless it is periodically serviced by the software. This allows the device to recover from a condition that has caused the system to be unstable.

The Asynchronous Timer AST combined with the 32KHz crystal oscillator supports powerful real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in counter mode or calendar mode.

The Frequency Meter FREQM allows accurate measuring of a clock frequency by comparing it to a known reference clock.

AT32UC3L016/32/64

The device includes six identical 16-bit Timer/Counter TC channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. The Pulse Width Modulation controller PWMA provides 8-bit PWM channels which can be synchronized and controlled from a common timer. One PWM channel is available for each I/O pin on the device, enabling applications that require multiple PWM outputs, such as LCD backlight control. The PWM channels can operate independently, with duty cycles set independently from each other, or in interlinked mode, with multiple channels changed at the same time. The AT32UC3L also features many communication interfaces for communication intensive applications like USART, SPI, or TWI. The USART supports different communication modes, like SPI Mode and LIN Mode. A general purpose 8-channel ADC is provided, as well as eight analog comparators AC . The ADC can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering up to 12-bit resolution. The ADC also provides an internal temperature sensor input channel. The analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. The Capacitive Touch CAT module senses touch on external capacitive touch sensors, using the QTouch technology. Capacitive touch sensors use no external mechanical components, unlike normal push buttons, and therefore demand less maintenance in the user application. The CAT module allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced. One touch sensor can be configured to operate autonomously without software interaction, allowing wakeup from sleep modes when activated. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys as well as Adjacent Key technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications. The AT32UC3L integrates a class 2+ Nexus On-chip Debug OCD System, with non-intrusive real-time trace, full-speed read/write memory access, in addition to basic runtime control. The NanoTrace interface enables trace feature for aWire- or JTAG-based debuggers. The single-pin aWire interface allows all features available through the JTAG interface to be accessed through the RESET pin, allowing the JTAG pins to be used for GPIO or peripherals.

AT32UC3L016/32/64

Overview

Block Diagram

Figure Block Diagram

TCK TDO TDI TMS

DATAOUT RESET_N

MCKO MDO[5..0] MSEO[1..0]

EVTI_N EVTO_N

JTAG INTERFACE
aWire

NEXUS CLASS 2+

AVR32UC CPU

MEMORY PROTECTION UNIT

INSTR

DATA

INTERFACE

MEMORY INTERFACE

LOCAL BUS INTERFACE

LOCAL BUS
If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 4-4 on page If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority

AT32UC3L016/32/64
than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4 on page Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floatingpoint unit.

AT32UC3L016/32/64

Table Priority and Handler Addresses for Events

Priority Handler Address

Name

Reset

Provided by OCD system

OCD Stop CPU

EVBA+0x00

Unrecoverable exception

EVBA+0x04

TLB multiple hit

EVBA+0x08

Bus error data fetch

EVBA+0x0C

Bus error instruction fetch

EVBA+0x10

Autovectored

Interrupt 3 request

Autovectored

Interrupt 2 request

Autovectored

Interrupt 1 request

Autovectored

Interrupt 0 request

EVBA+0x14

Instruction Address

EVBA+0x50

ITLB Miss

EVBA+0x18

ITLB Protection

EVBA+0x1C

Breakpoint

EVBA+0x20

Illegal Opcode

EVBA+0x24

Unimplemented instruction

EVBA+0x28

Privilege violation
Ordering Information
Table Ordering Information

Device AT32UC3L064 AT32UC3L032 AT32UC3L016
Ordering Code AT32UC3L064-AUTES AT32UC3L064-AUT AT32UC3L064-AUR AT32UC3L064-ZAUES AT32UC3L064-ZAUT AT32UC3L064-ZAUR AT32UC3L064-D3HES AT32UC3L064-D3HT AT32UC3L064-D3HR AT32UC3L032-AUT AT32UC3L032-AUR AT32UC3L032-ZAUT AT32UC3L032-ZAUR AT32UC3L032-D3HT AT32UC3L032-D3HR AT32UC3L016-AUT AT32UC3L016-AUR AT32UC3L016-ZAUT AT32UC3L016-ZAUR AT32UC3L016-D3HT AT32UC3L016-D3HR

Carrier Type ES Tray

Tape & Reel ES Tray

Tape & Reel ES Tray

Tape & Reel Tray

Tape & Reel Tray

Tape & Reel Tray

Tape & Reel Tray

Tape & Reel Tray

Tape & Reel Tray

Tape & Reel

Package TQFP 48

QFN 48

TLLGA 48 TQFP 48 QFN 48 TLLGA 48 TQFP 48 QFN 48 TLLGA 48

Package Type

Temperature Operating Range

JESD97 Classification E3

JESD97 Classification E4 Industrial -40°C to 85°C

JESD97 Classification E3

JESD97 Classification E4

JESD97 Classification E3

JESD97 Classification E4

AT32UC3L016/32/64

Errata

Processor and Architecture

Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions.

Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception will occur. Fix/Workaround Make a DTLB Protection Write exception handler which permits the interrupt request to be handled in privileged mode.

FLASHCDW

Flash self programming may fail in one wait state mode Writes in flash and user pages may fail if executing code is located in address space mapped to flash, and the flash controller is configured in one wait state mode the Flash Wait State bit in the Flash Control Register FCR.FWS is one . Fix/Workaround Solution 1 Configure the flash controller in zero wait state mode FCR.FWS=0 . Solution 2 Configure the HMATRIX master 1 CPU Instruction to use the unlimited burst length transfer mode MCFG1.ULBT=0 , and the HMATRIX slave 0 FLASHCDW to use the maximum slot cycle limit SCFG0.SLOT_CYCLE=255 .

Power Manager

Clock sources will not be stopped in Static mode if the difference between CPU and PBx division factor is larger than 4 If the division factor between the CPU/HSB and PBx frequencies is more than 4 when entering a sleep mode where the system RC oscillator RCSYS is turned off, the high speed clock sources will not be turned off. This will result in a significantly higher power consumption during the sleep mode. Fix/Workaround Before going to sleep modes where RCSYS is stopped, make sure the division factor between CPU/HSB and PBx frequencies is less than or equal to

Clock Failure Detector CFD can be issued while turning off the CFD While turning off the CFD, the CFD bit in the Status Register SR can be set. This will change the main clock source to RCSYS. Fix/Workaround Solution 1 Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch back to original main clock source. Solution 2 Only turn off the CFD while running the main clock on RCSYS.

Sleepwalking in idle and frozen sleep mode will mask all other PB clocks

SCIF AST

AT32UC3L016/32/64

If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walking, all PB clocks will be masked except the PB clock to the sleepwalking module. Fix/Workaround Mask all clock requests in the PM.PPCR register before going into idle or frozen mode.

The FLO lock bit FLOCR.LOCK does not work The FLO lock bit does not work and will always read as zero. Fix/Workaround Wait for 32 reference clock cycles after the tuner is enabled, then read the FLO.NOLOCK bit to check if it is set. If it is set, a lock can not be obtained for this configuration of reference clock and target ratio.

PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K is disabled. Fix/Workaround When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit. If this bit is 0 Follow normal procedures. 1 Ignore the PCLKSR.OSC32RDY and ISR.OSC32RDY bit. Use the Frequency Meter FREQM to determine if the OSC32K clock is ready. The OSC32K clock is ready when the FREQM measures a non-zero frequency.

The RC32K output on PA20 is not always permanently disabled The RC32K output on PA20 may sometimes re-appear. Fix/Workaround Before using RC32K for other purposes, the following procedure has to be followed in order to properly disable it - Run the CPU on RCSYS - Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT - Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as one - Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as zero.

Reset may set status bits in the AST If a reset occurs and the AST is enabled, the SR.ALARM0, SR.PER0, and SR.OVF bits may be set. Fix/Workaround If the part is reset and the AST is used, clear all bits in the Status Register before entering sleep mode.

AST wake signal is released one AST clock cycle after the BUSY bit is cleared After writing to the Status Clear Register SCR the wake signal is released one AST clock cycle after the BUSY bit in the Status Register SR.BUSY is cleared. If entering sleep mode directly after the BUSY bit is cleared the part will wake up immediately. Fix/Workaround Read the Wake Enable Register WER and write this value back to the same register. Wait for BUSY to clear before entering sleep mode.
Ordering Information Ordering code for TQFP ES changed from AT32UC3L064-AUES to AT32UC3L064-AUTES. TLLGA48 Tray option added.

Features and Description Added QTouch library support.

USART Description of unimplemented features removed.

Electrical Characteristics Power Consumption numbers updated. Flash timing numbers added.

Package and Pinout Added pinout figure for TLLGA48 package.

Package and Pinout, GPIO function multiplexing:TWIMS0-TWCK on PA20 removed. ADCIFB-

AD[3] on PA17 removed, number of ADC channels are 8, not

I/O Lines Considerations Added Following pins have high-drive capability PA02, PA06,

PA08, PA09, and PB01.

Some TWI0 pins are SMBUS compliant PA21, PB04, PB05 .

HMATRIX Masters PDCA is master 4, not master SAU is master 3, not master

SAU IDLE bit added in the Status Register.

PDCA Number of PDCA performance monitors is device dependent.

Peripheral Event System Chapter updated.

PM Bits in RCAUSE registers removed and renamed JTAGHARD and AWIREHARD renamed
to JTAG and AWIRE respectively, JTAG and AWIRE removed. BOD33 bit removed .

PM RCAUSE.BOD33 bit removed. SM33 reset will be detected as a POR reset.

PM WDT can be used as wake-up source if WDT is clocked from 32KHz oscillator.

PM Entering Shutdown mode description updated.

SCIF DFLL output frequency is 40-150MHz, not 20-150MHz or 30-150MHz.

AT32UC3L016/32/64
SCIF Temperature sensor is connected to ADC channel 9, not SCIF Updated the oscillator connection figure for OSC0 GPIO Removed unimplemented features pull-down, buskeeper, drive strength, slew rate, Schmidt trigger, open drain . SPI RDR.PCS field removed RDR[19:16] . TWIS Figures updated. ADCIFB The sample and hold time and the startup time formulas have been corrected ADC Configuration Register . ADCIFB Updated ADC signal names. ACIFB CONFW.WEVSRC is bit 8-10, CONFW.EWEVEN is bit CONF.EVENP and CONF.EVENN bits are swapped. CAT Matrix size is 16 by 8, not 18 by Electrical Characteristics General update. Mechanical Characteristics Added numbers for package drawings. Mechanical Characteristics In the TQFP-48 package drawing the Lead Coplanarity is 0.102mm, not 0.080mm. Ordering Information Ordering code for TLLGA-48 package updated.

AT32UC3L016/32/64

Table of Contents

Features 1 Description 3 2 Overview 5

Block Diagram Configuration Summary
3 Package and Pinout 7

Package Peripheral Multiplexing on I/O lines Signal Descriptions I/O Line Considerations
4 Processor and Architecture 18

Features AVR32 Architecture The AVR32UC CPU Programming Model Exceptions and Interrupts
5 Memories 32

Embedded Memories Physical Memory Map Peripheral Address Map CPU Local Bus Mapping
6 Supply and Startup Considerations 36

Supply Considerations Startup Considerations
7 Electrical Characteristics 41

Disclaimer Absolute Maximum Ratings* Supply Characteristics Maximum Clock Frequencies Power Consumption I/O Pin Characteristics Oscillator Characteristics

AT32UC3L016/32/64

Flash Characteristics Analog Characteristics Timing Characteristics
8 Mechanical Characteristics 73

Thermal Considerations Package Drawings Soldering Profile
9 Ordering Information 78 10 Errata 79

Table of i

Headquarters

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600

International

Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel 852 2245-6100 Fax 852 2722-1369

Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11

Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581

Product Contact

Web Site

Literature Requests

Technical Support

Sales Contact

Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
2011 Atmel Corporation. All rights reserved. Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

More datasheets: 333-2SURC/H3/S530-A4 | FJP9100TU | 831502B03900 | 7101P2-M | 7101P3-M | 7101R1-M | 7101R4-M | 7101P4-M | 410-300 | PD95-21B/TR10

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT32UC3L0-XPLD Datasheet file may be downloaded here without warranties.

Datasheet ID: AT32UC3L0-XPLD 519011