AT29C010A-90TU-T

AT29C010A-90TU-T Datasheet


The AT29C010A is a 5-volt-only in-system Flash programmable and erasable read only memory PEROM . Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW over the industrial temperature range. When the device is deselected, the CMOS standby current is less than 300µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.

Part Datasheet
AT29C010A-90TU-T AT29C010A-90TU-T AT29C010A-90TU-T (pdf)
Related Parts Information
AT29C010A-90JU-T AT29C010A-90JU-T AT29C010A-90JU-T
AT29C010A-70JU AT29C010A-70JU AT29C010A-70JU
AT29C010A-90TU AT29C010A-90TU AT29C010A-90TU
AT29C010A-90JU AT29C010A-90JU AT29C010A-90JU
AT29C010A-70TU AT29C010A-70TU AT29C010A-70TU
PDF Datasheet Preview
• Fast Read Access Time 70 ns
• 5-volt Only Reprogramming
• Sector Program Operation

Single Cycle Reprogram Erase and Program 1024 Sectors 128 Bytes/Sector Internal Address and Data Latches for 128 Bytes
• Two 8K Bytes Boot Blocks with Lockout
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Fast Sector Program Cycle Time 10 ms
• DATA Polling for End of Program Detection
• Low Power Dissipation 50 mA Active Current 300 µA CMOS Standby Current
• Typical Endurance > 10,000 Cycles
• Single 5V ±10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
• Green Pb/Halide-free Packaging Option

The AT29C010A is a 5-volt-only in-system Flash programmable and erasable read only memory PEROM . Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW over the industrial temperature range. When the device is deselected, the CMOS standby current is less than 300µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.

To allow for simple in-system reprogrammability, the AT29C010A does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C010A is performed on a sector basis 128 bytes of data are loaded into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can begin.
1-megabit 128K x 8 5-volt Only Flash Memory

AT29C010A

Not Recommended for New Design

Contact Atmel to discuss the latest design in trends and options

Pin Configurations

Pin Name A0 - A16 CE OE WE I/O0 - I/O7 NC
32-lead PLCC Top View

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect
4 A12 3 A15 2 A16 1 NC 32 VCC 31 WE 30 NC

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13
29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7

I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20
32-lead TSOP Type 1 Top View

A11 1 A9 2 A8 3

A13 4 A14 5 NC 6 WE 7 VCC 8 NC 9 A16 10 A15 11 A12 12

A7 13 A6 14 A5 15 A4 16
32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3
2 AT29C010A

Block Diagram

AT29C010A

Device Operation

Read

The AT29C010A is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

Byte Load

Byte loads are used to enter the 128 bytes of a sector to be programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.

Program

The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. The data in any byte that is not loaded during the programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE or CE within 150 of the low to high transition of WE or CE of the preceding byte. If a high to low transition is not detected within 150 of the last low to high transition, the load period will end and the internal programming period will start. A7 to A16 specify the sector address. The sector address must be valid during each high to low transition of WE or CE . A0 to A6 specify the byte address within the sector. The bytes may be loaded in any order sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation.

Software Data Protection

A software controlled data protection feature is available on the AT29C010A. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user when
shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the sector program timing specifications. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions.

Once set, software data protection will remain active unless the disable command sequence is issued.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device however, for the duration of tWC, a read operation will effectively be a polling operation.

After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 128 bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation.

Hardware Data Protection

Hardware features protect against inadvertent programs to the AT29C010A in the following ways a VCC sense if VCC is below 3.8V typical , the program function is inhibited b VCC power on delay once VCC has reached the VCC sense level, the device will automatically time out 5 ms typical before programming c Program inhibit holding any one of OE low, CE high or WE high inhibits program cycles and d Noise of less than 15 ns typical on the WE or CE inputs will not initiate a program cycle.

Product Identification
Ordering Information

Green Package Option Pb/Halide-free
tACC

ICC mA

Active

Standby
Ordering Code

AT29C010A-70JU

AT29C010A-70TU

AT29C010A-90JU

AT29C010A-90TU

AT29C010A

Package 32J 32T 32J 32T

Operation Range

Industrial -40 to 85C

Package Type
32-lead, Plastic J-leaded Chip Carrier PLCC
32-lead, Thin Small Outline Package TSOP

Packaging Information
32J PLCC

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 45 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
16 AT29C010A
32T TSOP

PIN 1

AT29C010A
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation BD. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e

MIN NOM MAX

BASIC
More datasheets: 7343-2UYC/S400-A9 | FQP44N08 | 17100-600 | FDFS2P103A | 1257 | B39431B3750U310 | FFD06UP20S | ATA6826N-TUQY | ATA6826-TUSY | ATA6826-TUQY


Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT29C010A-90TU-T Datasheet file may be downloaded here without warranties.

Datasheet ID: AT29C010A-90TU-T 518988