AT28C64E-12TU

AT28C64E-12TU Datasheet


AT28C64E

Part Datasheet
AT28C64E-12TU AT28C64E-12TU AT28C64E-12TU (pdf)
Related Parts Information
AT28C64E-12JU AT28C64E-12JU AT28C64E-12JU
AT28C64E-12SU AT28C64E-12SU AT28C64E-12SU
PDF Datasheet Preview
• Fast Read Access Time 120 ns
• Fast Byte Write 200 µs
• Self-timed Byte Write Cycle

Internal Address and Data Latches Internal Control Timer Automatic Clear Before Write
• Direct Microprocessor Control READY/BUSY Open Drain Output DATA Polling
• Low Power 30 mA Active Current 100 µA CMOS Standby Current
• High Reliability Endurance 105 Cycles Data Retention 10 Years
• 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-wide Pinout
• Industrial Temperature Ranges
• Green Pb/Halide-Free Packaging Option
64K 8K x 8 Parallel EEPROMs

AT28C64E

The AT28C64E is a low-power, high-performance 8,192 words by 8-bit nonvolatile electrically erasable and programmable read-only memory with popular, easy-to-use features. The device is manufactured with Atmel’s reliable nonvolatile technology.

The AT28C64E is accessed like a Static RAM for the read or write cycles without the need for external components. During a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of a write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. The device includes two methods for detecting the end of a write cycle, level detection of RDY/BUSY unless pin 1 is N.C. and DATA Polling of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin.

The CMOS technology offers fast access times of 120 ns at low power dissipation. When the chip is deselected, the standby current is less than 100 µA.

Atmel’s AT28C64E has additional features to ensure high quality and manufacturability. The device utilizes error correction internally for extended endurance and for improved data retention characteristics. An extra 32 bytes of EEPROM are available for device identification or tracking.

Pin Configurations

Pin Name A0 - A12 CE OE WE I/O0 - I/O7 RDY/BUSY NC DC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs Ready/Busy Output No Connect Don’t Connect

PDIP, SOIC Top View

RDY/BUSY or NC 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O0 11 I/O1 12 I/O2 13 GND 14
28 VCC 27 WE 26 NC 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3

TSOP Top View

OE 1 A11 2

A9 3 A8 4 NC 5 WE 6 VCC 7 RDY/BUSY or NC 8 A12 9 A7 10 A6 11 A5 12 A4 13 A3 14

LCC, PLCC Top View
28 A10 27 CE 26 I/O7 25 I/O6 24 I/O5 23 I/O4 22 I/O3 21 GND 20 I/O2 19 I/O1 18 I/O0 17 A0 16 A1 15 A2
4 A7 3 A12 2 RDY/BUSY or NC 1 DC 32 VCC 31 WE 30 NC

A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 I/O0 13
29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6

I/O1 14 I/O2 15 VSS 16 DC 17 I/O3 18 I/O4 19 I/O5 20

Note PLCC package pins 1 and 17 are DON’T CONNECT.
2 AT28C64E

Block Diagram

AT28C64E

Absolute Maximum Ratings*

Temperature under Bias -55°C to +125°C

Storage Temperature -65°C to +150°C

All Input Voltages including NC Pins with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V

Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

Device Operation

Read

The AT28C64E is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in a high impedance state whenever CE or OE is high. This dual line control gives designers increased flexibility in preventing bus contention.

Byte Write

Writing data into the AT28C64E is similar to writing into a Static RAM. A low pulse on the WE or CE input with OE high and CE or WE low respectively initiates a byte write. The address location is latched on the falling edge of WE or CE the new data is latched on the rising edge. Internally, the device performs a self-clear before write. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.

Fast Byte Write
Ordering Information

Standard Package
tACC

ICC mA

Active Standby
Ordering Code

AT28C64E-12JI AT28C64E-12PI AT28C64E-12SI AT28C64E-12TI

Green Package Pb/Halide-free
tACC

ICC mA

Active Standby
Ordering Code

AT28C64E-12JU

AT28C64E-12PU

AT28C64E-12SU

AT28C64E-12TU

Package Type

Package 32J 28P6 28S 28T

Package 32J 28P6 28S 28T
32J 28P6 28S 28T
32-lead, Plastic J-leaded Chip Carrier PLCC 28-lead, Wide, Plastic Dull Inline Package PDIP 28-lead, Wide, Plastic Gull Wing, Small Outline SOIC 28-lead, Plastic Thin Small Outline Package TSOP

Valid Part Numbers

The following table lists standard products that can be ordered.

Device Numbers

Speed

Package and Temperature Combinations

AT28C64E

JI, JU, PI, PU, SI, SU, TI, TU

Die Products

Reference Section Parallel EEPROM Die Products

AT28C64E

Operation Range Industrial
-40° C to 85° C

Operation Range Industrial
-40° C to 85° C

Packaging Information
32J PLCC

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
12 AT28C64E
28P6 PDIP
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Datasheet ID: AT28C64E-12TU 518971